| commit | 5a69943136c65ef7576a24575e0e514cd2130eb3 | [log] [tgz] |
|---|---|---|
| author | pu.wang <pu.wang@verisilicon.com> | Tue Jul 01 17:55:05 2025 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Thu Jul 10 16:19:47 2025 -0700 |
| tree | 4c9d13dd2ffee24dde044c7ee819504942b267c0 | |
| parent | 096bfb919e8c58d6e6cc790f0bba079e5f27dc07 [diff] |
Update exclusiton files Change-Id: I7a00aa008eb32472cf653c2c5c7ab928b11b7324
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog