Buildify cocotb, verilator-sim and chisel/common

Change-Id: If145679b87c8f6748d87920da250c7d884de0820

hdl/chisel/src/common/BUILD

diff --git a/hdl/chisel/src/common/BUILD b/hdl/chisel/src/common/BUILD
index 40605d1..45695b8 100644
--- a/hdl/chisel/src/common/BUILD
+++ b/hdl/chisel/src/common/BUILD
@@ -52,7 +52,7 @@
 chisel_library(
     name = "aligner",
     srcs = [
-        "Aligner.scala"
+        "Aligner.scala",
     ],
     resources = [
         "//hdl/verilog/rvv/design:Aligner.sv",
@@ -107,8 +107,8 @@
     ],
     visibility = ["//visibility:public"],
     deps = [
-        ":library",
         ":circular_buffer_multi",
+        ":library",
     ],
 )
 
@@ -185,13 +185,13 @@
 
 chisel_test(
     name = "scatter_gather_test",
+    size = "large",
     srcs = [
         "ScatterGatherTest.scala",
     ],
     deps = [
         ":scatter_gather",
     ],
-    size = "large",
 )
 
 chisel_library(

tests/cocotb/BUILD

diff --git a/tests/cocotb/BUILD b/tests/cocotb/BUILD
index dedacec..fe9dc5e 100644
--- a/tests/cocotb/BUILD
+++ b/tests/cocotb/BUILD
@@ -17,7 +17,6 @@
 load("//rules:coco_tb.bzl", "cocotb_test_suite", "verilator_cocotb_model")
 load("//rules:kelvin_v2.bzl", "kelvin_v2_binary")
 load("//rules:utils.bzl", "template_rule")
-
 load(
     "//tests/cocotb:build_defs.bzl",
     "VCS_BUILD_ARGS",
@@ -115,25 +114,35 @@
     cocotb_test_suite,
     {
         "core_mini_axi_sim_cocotb": {
-            "tests_kwargs": dict(CORE_MINI_AXI_SIM_COMMON_TEST_KWARGS, hdl_toplevel = "CoreMiniAxi"),
+            "tests_kwargs": dict(
+                CORE_MINI_AXI_SIM_COMMON_TEST_KWARGS,
+                hdl_toplevel = "CoreMiniAxi",
+            ),
             "vcs_verilog_sources": ["//hdl/chisel/src/kelvin:core_mini_axi_cc_library_verilog"],
             "verilator_model": ":core_mini_axi_model",
             "testcases": CORE_MINI_AXI_SIM_TESTCASES,
             "testcases_vname": "CORE_MINI_AXI_SIM_TESTCASES",
         },
         "rvv_core_mini_axi_sim_cocotb": {
-            "tests_kwargs": dict(CORE_MINI_AXI_SIM_COMMON_TEST_KWARGS, hdl_toplevel = "RvvCoreMiniAxi", tags = ["manual"]),
+            "tests_kwargs": dict(
+                CORE_MINI_AXI_SIM_COMMON_TEST_KWARGS,
+                hdl_toplevel = "RvvCoreMiniAxi",
+                tags = ["manual"],
+            ),
             "vcs_verilog_sources": ["//hdl/chisel/src/kelvin:rvv_core_mini_axi_cc_library_verilog"],
             "verilator_model": ":rvv_core_mini_axi_model",
             "testcases": RVV_CORE_MINI_AXI_SIM_TESTCASES,
             "testcases_vname": "RVV_CORE_MINI_AXI_SIM_TESTCASES",
         },
     },
-    simulators = ["verilator", "vcs"],
-    vcs_data = COCOTB_TEST_BINARY_TARGETS + [":coverage_exclude.cfg"],
+    simulators = [
+        "verilator",
+        "vcs",
+    ],
     vcs_build_args = VCS_BUILD_ARGS,
-    vcs_test_args = VCS_TEST_ARGS,
+    vcs_data = COCOTB_TEST_BINARY_TARGETS + [":coverage_exclude.cfg"],
     vcs_defines = VCS_DEFINES,
+    vcs_test_args = VCS_TEST_ARGS,
 )
 
 # BEGIN_TESTCASES_FOR_core_mini_axi_debug_cocotb
@@ -258,15 +267,15 @@
             ":registers.elf",
         ],
     },
-    vcs_data = [
-            ":fptr.elf",
-            ":math.elf",
-            ":noop.elf",
-            ":registers.elf",
-    ] + [":coverage_exclude.cfg"],
     vcs_build_args = VCS_BUILD_ARGS,
-    vcs_test_args = VCS_TEST_ARGS,
+    vcs_data = [
+        ":fptr.elf",
+        ":math.elf",
+        ":noop.elf",
+        ":registers.elf",
+    ] + [":coverage_exclude.cfg"],
     vcs_defines = VCS_DEFINES,
+    vcs_test_args = VCS_TEST_ARGS,
     vcs_verilog_sources = ["//hdl/chisel/src/kelvin:core_mini_axi_debug_cc_library_verilog"],
     verilator_model = ":core_mini_debug_axi_model",
 )
@@ -293,10 +302,10 @@
         "data": ["//tests/cocotb/rvv:rvv_assem_tests"],
         "size": "large",
     },
-    vcs_data = ["//tests/cocotb/rvv:rvv_assem_tests"] + [":coverage_exclude.cfg"],
     vcs_build_args = VCS_BUILD_ARGS,
-    vcs_test_args = VCS_TEST_ARGS,
+    vcs_data = ["//tests/cocotb/rvv:rvv_assem_tests"] + [":coverage_exclude.cfg"],
     vcs_defines = VCS_DEFINES,
+    vcs_test_args = VCS_TEST_ARGS,
     vcs_verilog_sources = ["//hdl/chisel/src/kelvin:rvv_core_mini_axi_cc_library_verilog"],
     verilator_model = ":rvv_core_mini_axi_model",
 )
@@ -409,10 +418,10 @@
         "size": "large",
         "timeout": "eternal",
     },
-    vcs_data = ["//tests/cocotb/rvv/load_store:rvv_load_store_tests"] + [":coverage_exclude.cfg"],
     vcs_build_args = VCS_BUILD_ARGS,
-    vcs_test_args = VCS_TEST_ARGS,
+    vcs_data = ["//tests/cocotb/rvv/load_store:rvv_load_store_tests"] + [":coverage_exclude.cfg"],
     vcs_defines = VCS_DEFINES,
+    vcs_test_args = VCS_TEST_ARGS,
     vcs_verilog_sources = ["//hdl/chisel/src/kelvin:rvv_core_mini_axi_cc_library_verilog"],
     verilator_model = ":rvv_core_mini_axi_model",
 )
@@ -438,10 +447,10 @@
         "data": ["//tests/cocotb/rvv/arithmetics:rvv_arith_tests"],
         "size": "large",
     },
-    vcs_data = ["//tests/cocotb/rvv/arithmetics:rvv_arith_tests"] + [":coverage_exclude.cfg"],
     vcs_build_args = VCS_BUILD_ARGS,
-    vcs_test_args = VCS_TEST_ARGS,
+    vcs_data = ["//tests/cocotb/rvv/arithmetics:rvv_arith_tests"] + [":coverage_exclude.cfg"],
     vcs_defines = VCS_DEFINES,
+    vcs_test_args = VCS_TEST_ARGS,
     vcs_verilog_sources = ["//hdl/chisel/src/kelvin:rvv_core_mini_axi_cc_library_verilog"],
     verilator_model = ":rvv_core_mini_axi_model",
 )
@@ -480,10 +489,10 @@
         "data": ["//tests/cocotb/rvv/ml_ops:rvv_mlop_tests"],
         "size": "large",
     },
-    vcs_data = ["//tests/cocotb/rvv/ml_ops:rvv_mlop_tests"] + [":coverage_exclude.cfg"],
     vcs_build_args = VCS_BUILD_ARGS,
-    vcs_test_args = VCS_TEST_ARGS,
+    vcs_data = ["//tests/cocotb/rvv/ml_ops:rvv_mlop_tests"] + [":coverage_exclude.cfg"],
     vcs_defines = VCS_DEFINES,
+    vcs_test_args = VCS_TEST_ARGS,
     vcs_verilog_sources = ["//hdl/chisel/src/kelvin:rvv_core_mini_axi_cc_library_verilog"],
     verilator_model = ":rvv_core_mini_axi_model",
 )

tests/verilator_sim/BUILD

diff --git a/tests/verilator_sim/BUILD b/tests/verilator_sim/BUILD
index f3789fe..c3744fa 100644
--- a/tests/verilator_sim/BUILD
+++ b/tests/verilator_sim/BUILD
@@ -79,8 +79,9 @@
 )
 
 CORE_MINI_AXI_TB_CC_LIBRARY_COMMON_SRCS = [
-        "kelvin/core_mini_axi_tb.cc",
+    "kelvin/core_mini_axi_tb.cc",
 ]
+
 CORE_MINI_AXI_TB_CC_LIBRARY_COMMON_DEPS = [
     ":elf",
     ":sim_libs",
@@ -94,6 +95,7 @@
     "@com_google_absl//absl/status",
     "@libsystemctlm_soc",
 ]
+
 template_rule(
     cc_library,
     {
@@ -143,6 +145,7 @@
     "@com_google_absl//absl/log",
     "@com_google_absl//absl/log:check",
 ]
+
 template_rule(
     cc_binary,
     {