Address STARC05-1.3.1.3 lint issues.

Separate resettable and non-resettable registers into different
always_ff blocks.

Change-Id: I5f1835b0274809d5a96a1f9931b945d13e18934b

hdl/chisel/src/kelvin/BUILD

diff --git a/hdl/chisel/src/kelvin/BUILD b/hdl/chisel/src/kelvin/BUILD
index 51ee1e7..8b3d1c3 100644
--- a/hdl/chisel/src/kelvin/BUILD
+++ b/hdl/chisel/src/kelvin/BUILD
@@ -113,7 +113,6 @@
         "//hdl/verilog/rvv/common:edff_2d.sv",
         "//hdl/verilog/rvv/common:multi_fifo.sv",
         "//hdl/verilog/rvv/design:Aligner.sv",
-        "//hdl/verilog/rvv/design:MultiFifo.sv",
         "//hdl/verilog/rvv/design:RvvCore.sv",
         "//hdl/verilog/rvv/design:RvvFrontEnd.sv",
         "//hdl/verilog/rvv/design:rvv_backend.sv",

hdl/chisel/src/kelvin/rvv/RvvCore.scala

diff --git a/hdl/chisel/src/kelvin/rvv/RvvCore.scala b/hdl/chisel/src/kelvin/rvv/RvvCore.scala
index cde9738..de49247 100644
--- a/hdl/chisel/src/kelvin/rvv/RvvCore.scala
+++ b/hdl/chisel/src/kelvin/rvv/RvvCore.scala
@@ -405,7 +405,6 @@
   addResource("hdl/verilog/rvv/common/edff_2d.sv")
   addResource("hdl/verilog/rvv/common/multi_fifo.sv")
   addResource("hdl/verilog/rvv/design/Aligner.sv")
-  addResource("hdl/verilog/rvv/design/MultiFifo.sv")
   addResource("hdl/verilog/rvv/design/RvvFrontEnd.sv")
   addResource("hdl/verilog/rvv/design/rvv_backend_alu_unit_addsub.sv")
   addResource("hdl/verilog/rvv/design/rvv_backend_alu_unit_execution_p1.sv")

hdl/verilog/rvv/design/MultiFifo.sv

diff --git a/hdl/verilog/rvv/design/MultiFifo.sv b/hdl/verilog/rvv/design/MultiFifo.sv
index 27821cd..0182774 100644
--- a/hdl/verilog/rvv/design/MultiFifo.sv
+++ b/hdl/verilog/rvv/design/MultiFifo.sv
@@ -64,17 +64,19 @@
     end else begin
       head <= WrapAroundSum(head, valid_in);
       tail <= WrapAroundSum(tail, ready_out);
-
-      // Update buffer
-      for (int i = 0; i < N; i++) begin
-        if (i < valid_in) begin
-          buffer[WrapAroundSum(head, i)] <= data_in[i];
-        end
-      end
       m_fill_level <= m_fill_level + valid_in - ready_out;
     end
   end
 
+  always_ff @(posedge clk) begin
+    // Update buffer
+    for (int i = 0; i < N; i++) begin
+      if (i < valid_in) begin
+        buffer[WrapAroundSum(head, i)] <= data_in[i];
+      end
+    end
+  end
+
   always_comb begin
     for (int i = 0; i < N; i++) begin
       data_out[i] = buffer[WrapAroundSum(tail, i)];

hdl/verilog/rvv/design/RvvFrontEnd.sv

diff --git a/hdl/verilog/rvv/design/RvvFrontEnd.sv b/hdl/verilog/rvv/design/RvvFrontEnd.sv
index facb7d3..97d7e67 100644
--- a/hdl/verilog/rvv/design/RvvFrontEnd.sv
+++ b/hdl/verilog/rvv/design/RvvFrontEnd.sv
@@ -118,11 +118,16 @@
       for (int i = 0; i < N; i++) begin
         valid_inst_q[i] <= inst_accepted[i];
         valid_inst_count_q <= valid_inst_count_d;
-        inst_q[i] <= inst_data_i[i];
       end
     end
   end
 
+  always_ff @(posedge clk) begin
+    for (int i = 0; i < N; i++) begin
+      inst_q[i] <= inst_data_i[i];
+    end
+  end
+
   // Update configuration architectural state
   RVVConfigState inst_config_state [N:0];
   logic is_setvl [N-1:0];
@@ -199,11 +204,14 @@
   always_ff @(posedge clk or negedge rstn) begin
     if (!rstn) begin
       config_state_q.vill <= 1;  // Config is illegal on reset.
+      config_state_q.vl <= 16;
+      config_state_q.vstart <= 0;
       config_state_q.ma <= 0;
       config_state_q.ta <= 0;
+      config_state_q.xrm <= RNU;
+      config_state_q.xsat <= 0;
       config_state_q.sew <= SEW8;
       config_state_q.lmul <= LMUL1;
-      config_state_q.vl <= 16;
     end else begin
       // Update config state next cycle
       config_state_q <= inst_config_state[N];