Initialize several registers to 0

-Prevents X prop seen in kelvin_hello_world DV

Change-Id: I0044f7456d4495900582d075a6d055a9e551d962

hdl/chisel/src/kelvin/scalar/Dvu.scala

diff --git a/hdl/chisel/src/kelvin/scalar/Dvu.scala b/hdl/chisel/src/kelvin/scalar/Dvu.scala
index 5ae0353..1e73146 100644
--- a/hdl/chisel/src/kelvin/scalar/Dvu.scala
+++ b/hdl/chisel/src/kelvin/scalar/Dvu.scala
@@ -75,7 +75,7 @@
   val signed2r = Reg(Bool())
   val divide2  = Reg(Bool())
 
-  val count = Reg(UInt(6.W))
+  val count  = RegInit(0.U(6.W))
 
   val divide = Reg(UInt(32.W))
   val remain = Reg(UInt(32.W))

hdl/chisel/src/kelvin/vector/VInst.scala

diff --git a/hdl/chisel/src/kelvin/vector/VInst.scala b/hdl/chisel/src/kelvin/vector/VInst.scala
index 2da7fe6..26efbfc 100644
--- a/hdl/chisel/src/kelvin/vector/VInst.scala
+++ b/hdl/chisel/src/kelvin/vector/VInst.scala
@@ -118,7 +118,7 @@
   // ---------------------------------------------------------------------------
   // Vector Interface.
   val vvalid = RegInit(false.B)
-  val vinstValid = Reg(Vec(4, Bool()))
+  val vinstValid = RegInit(VecInit(Seq.fill(4)(false.B)))
   val vinstInst = Reg(Vec(4, UInt(32.W)))
   val nxtVinstValid = Wire(Vec(4, Bool()))