blob: 85ee4f85e643ce4cd915991e9f93eed36c27f8ce [file] [log] [blame]
load("@rules_hdl//verilog:providers.bzl", "VerilogInfo", "verilog_library")
verilog_library(
name = "clock_gate",
srcs = ["ClockGate.v"],
visibility = ["//visibility:public"],
)
verilog_library(
name = "sram_1rw_256x256",
srcs = ["Sram_1rw_256x256.v"],
visibility = ["//visibility:public"],
)
verilog_library(
name = "sram_1rw_256x288",
srcs = ["Sram_1rwm_256x288.v"],
visibility = ["//visibility:public"],
)