third_party/ip/lowrisc/prim_clock_gating.sv

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

// Abstract primitives wrapper.
//
// This file is a stop-gap until the DV file list is generated by FuseSoC.
// Its contents are taken from the file which would be generated by FuseSoC.
// https://github.com/lowRISC/ibex/issues/893

package lowrisc_prim_pkg;

  // Implementation target specialization
  typedef enum integer {
    ImplGeneric,
    ImplXilinx
  } impl_e;
endpackage : lowrisc_prim_pkg

`ifndef LOWRISC_PRIM_DEFAULT_IMPL
  `ifdef FPGA_XILINX
    `define LOWRISC_PRIM_DEFAULT_IMPL lowrisc_prim_pkg::ImplXilinx
  `else
    `define LOWRISC_PRIM_DEFAULT_IMPL lowrisc_prim_pkg::ImplGeneric
  `endif
`endif

module lowrisc_prim_clock_gating (
  input        clk_i,
  input        en_i,
  input        test_en_i,
  output logic clk_o
);
  parameter lowrisc_prim_pkg::impl_e Impl = `LOWRISC_PRIM_DEFAULT_IMPL;

  if (Impl == lowrisc_prim_pkg::ImplGeneric) begin : gen_generic
`ifndef SYNTHESIS
    lowrisc_prim_generic_clock_gating u_impl_generic (
      .*
    );
`endif
  end else if (Impl == lowrisc_prim_pkg::ImplXilinx) begin : gen_xilinx
`ifdef FPGA_XILINX
    lowrisc_prim_xilinx_clock_gating u_impl_xilinx (
      .*
    );
`endif
  end else begin : gen_failure
    // TODO: Find code that works across tools and causes a compile failure
  end

endmodule