| commit | f7bfda132eb8392d75dc7e4ceafc6fa62d9509f3 | [log] [tgz] |
|---|---|---|
| author | Zhidong.Liang <Zhidong.Liang@verisilicon.com> | Fri Jun 27 11:24:11 2025 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Thu Jul 10 16:19:47 2025 -0700 |
| tree | 48058390c82cf2ec730152df20b9c4bf052114e9 | |
| parent | cf76555ae13cdada6b0761f84771e4ad9e467e16 [diff] |
update multiple 1-bit flops to multi-bit flops. Change-Id: Idebda7fe31ebd919a429bac93acf605a2b5ac0e1
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog