| commit | cf76555ae13cdada6b0761f84771e4ad9e467e16 | [log] [tgz] |
|---|---|---|
| author | pu.wang <pu.wang@verisilicon.com> | Wed Jun 25 13:41:23 2025 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Thu Jul 10 16:19:47 2025 -0700 |
| tree | 28083a57f54e7d1df4e29da1b0bea534b5330d2c | |
| parent | 15d3edf029b6583ff7398b42216f9404469dc3d2 [diff] |
Update exclusoon files. Update tb connection with rvvbackend Change-Id: If7dc29691d43dd889ffeddc707b7a3803312101e
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog