commit | 088a57782dbdf57660439a9b53b6cdda89d2d2fb | [log] [tgz] |
---|---|---|
author | pu.wang <pu.wang@verisilicon.com> | Fri Jul 25 17:52:41 2025 +0800 |
committer | Derek Chow <derekjchow@google.com> | Tue Aug 05 10:51:45 2025 -0700 |
tree | 1f9c492f77419582f13f5f7d1718be5227adcf88 | |
parent | 8dc9126d8ae0da44219fa3f04f0149968641732c [diff] |
update monitor in rvv backend tb Change-Id: I1b7b6de2c4b25f32340b420fa5ca7904f466fc44
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog