| commit | 8dc9126d8ae0da44219fa3f04f0149968641732c | [log] [tgz] |
|---|---|---|
| author | pu.wang <pu.wang@verisilicon.com> | Tue Jul 22 16:26:10 2025 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Tue Aug 05 10:51:36 2025 -0700 |
| tree | ee7e6ab6a2974f2d1d164c3530f70595bcefa391 | |
| parent | 7f34b1728279dec1d6f6159a1314557edaefc5e2 [diff] |
Update rvv_backend exclusion file Change-Id: I6aacbe3c238ec8d4c3f36fd6172a2851524b917b
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog