Bundle Kelvin's memory interface
- Create a KelvinMemIO Bundle, containing the memory interface for
Kelvin. This simplifies connecting the memory interface to a memory in
Chisel.
Change-Id: Ib12a3aa3f1b2572f1dca8cc6d854b534eb0617d8
diff --git a/hdl/chisel/src/matcha/Kelvin.scala b/hdl/chisel/src/matcha/Kelvin.scala
index 65c8da0..31efda2 100644
--- a/hdl/chisel/src/matcha/Kelvin.scala
+++ b/hdl/chisel/src/matcha/Kelvin.scala
@@ -19,6 +19,19 @@
import common._
import _root_.circt.stage.ChiselStage
+class KelvinMemIO(p: kelvin.Parameters) extends Bundle {
+ val cvalid = (Output(Bool()))
+ val cready = (Input(Bool()))
+ val cwrite = (Output(Bool()))
+ val caddr = (Output(UInt(p.axiSysAddrBits.W)))
+ val cid = (Output(UInt(p.axiSysIdBits.W)))
+ val wdata = (Output(UInt(p.axiSysDataBits.W)))
+ val wmask = (Output(UInt((p.axiSysDataBits / 8).W)))
+ val rvalid = (Input(Bool()))
+ val rid = (Input(UInt(p.axiSysIdBits.W)))
+ val rdata = (Input(UInt(p.axiSysDataBits.W)))
+}
+
object Kelvin {
def apply(p: kelvin.Parameters): Kelvin = {
return Module(new Kelvin(p))
@@ -30,16 +43,7 @@
val clk_i = IO(Input(Clock()))
val rst_ni = IO(Input(AsyncReset()))
- val cvalid = IO(Output(Bool()))
- val cready = IO(Input(Bool()))
- val cwrite = IO(Output(Bool()))
- val caddr = IO(Output(UInt(p.axiSysAddrBits.W)))
- val cid = IO(Output(UInt(p.axiSysIdBits.W)))
- val wdata = IO(Output(UInt(p.axiSysDataBits.W)))
- val wmask = IO(Output(UInt((p.axiSysDataBits / 8).W)))
- val rvalid = IO(Input(Bool()))
- val rid = IO(Input(UInt(p.axiSysIdBits.W)))
- val rdata = IO(Input(UInt(p.axiSysDataBits.W)))
+ val mem = IO(new KelvinMemIO(p))
val clk_freeze = IO(Input(Bool()))
val ml_reset = IO(Input(Bool()))
@@ -118,16 +122,16 @@
// -------------------------------------------------------------------------
// SRAM bridge.
- cvalid := bus.io.out.cvalid
- bus.io.out.cready := cready
- cwrite := bus.io.out.cwrite
- caddr := bus.io.out.caddr
- cid := bus.io.out.cid
- wdata := bus.io.out.wdata
- wmask := bus.io.out.wmask
- bus.io.out.rvalid := rvalid
- bus.io.out.rid := rid
- bus.io.out.rdata := rdata
+ mem.cvalid := bus.io.out.cvalid
+ bus.io.out.cready := mem.cready
+ mem.cwrite := bus.io.out.cwrite
+ mem.caddr := bus.io.out.caddr
+ mem.cid := bus.io.out.cid
+ mem.wdata := bus.io.out.wdata
+ mem.wmask := bus.io.out.wmask
+ bus.io.out.rvalid := mem.rvalid
+ bus.io.out.rid := mem.rid
+ bus.io.out.rdata := mem.rdata
// -------------------------------------------------------------------------
// Command interface.
diff --git a/tests/verilator_sim/matcha/kelvin_tb.cc b/tests/verilator_sim/matcha/kelvin_tb.cc
index fe1a765..5211117 100644
--- a/tests/verilator_sim/matcha/kelvin_tb.cc
+++ b/tests/verilator_sim/matcha/kelvin_tb.cc
@@ -78,16 +78,16 @@
core.slog_addr(slog_addr);
core.slog_data(slog_data);
- core.cvalid(cvalid);
- core.cready(cready);
- core.cwrite(cwrite);
- core.caddr(caddr);
- core.cid(cid);
- core.wdata(wdata);
- core.wmask(wmask);
- core.rvalid(rvalid);
- core.rid(rid);
- core.rdata(rdata);
+ core.mem_cvalid(cvalid);
+ core.mem_cready(cready);
+ core.mem_cwrite(cwrite);
+ core.mem_caddr(caddr);
+ core.mem_cid(cid);
+ core.mem_wdata(wdata);
+ core.mem_wmask(wmask);
+ core.mem_rvalid(rvalid);
+ core.mem_rid(rid);
+ core.mem_rdata(rdata);
mif.clock(tb.clock);
mif.reset(tb.reset);
