| commit | 01727e64cd6a1437629b52ef0414e89d47079822 | [log] [tgz] |
|---|---|---|
| author | mingzhe.chen <mingzhe.chen@verisilicon.com> | Mon Jan 20 16:35:15 2025 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Thu Mar 06 14:56:41 2025 -0800 |
| tree | 9e0958260f6f0a4eee61990c40441307be2a55c6 | |
| parent | bc08a803a4c5ed553f96ce8d4051f83e3f8f3096 [diff] |
Fix vsmul overflow issue, the value was a typo Change-Id: I2d20e5d2646bd6f2cda4ce1e9442eab655239b72
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog