docs: Update doc with new targets
Update the doc description to reflect the new tock targets and the new
test_mlexecute target
Change-Id: I89ec752318866813e2e5bc8356d74ca891862c97
diff --git a/BuildTargetsExplained.md b/BuildTargetsExplained.md
index ad0c3f6..4de5b0c 100644
--- a/BuildTargetsExplained.md
+++ b/BuildTargetsExplained.md
@@ -5,27 +5,29 @@
## Build targets
-| Target | Source | Output | Description |
-| :----------------| :-------------------------------| :----------------------| :------------------------------------------------------------|
-| prereqs | | | Install build prerequisites |
-| tools | | cache | Install RISCV compiler and emulator tools, |
-| | | out/host | including Rust, GCC, CLANG, `verilator`, `qemu`, `renode` |
-| kata | kata/ | out/kata | SMC seL4 and user space applications |
-| tock | sw/tock/boards/opentitan-matcha | out/ tock | The operating system running on the security core, |
-| | sw/libtock-rs | out/libtock-rs | and its Rust library |
-| multihart_boot_rom | sw/multihart_boot_rom | out/shodan_boot_rom | Shodan boot rom |
-| springbok | sw/vec | out/springbok | Vector core BSP and RVV test code |
-| iree_compiler | | out/host/iree_compiler | IREE host compiler |
-| iree_runtime | toolchain/iree | out/springbok_iree | IREE runtime applications |
-| | sw/vec_iree | | |
-| iree | | | Shorthand for `iree_compiler` and `iree_runtime` |
-| opentitan_sw_all | hw/opentitan | out/opentitan | HW testing binaries |
-| qemu | toolchain/ristv-qemu | out/host/qemu | QEMU emulator |
-| renode | sim/renode | out/host/renode | Renode emulator |
-| verilator | sim/verilator | out/host/verilator | System Verilog HW emulator |
-| simulate | | | E2E build and launch renode simulation. |
-| | | | Targets include `tock`, `kata`, `multihart_boot_rom`, `iree` |
-| debug-simulation | | | Debug version of `simulate` |
+| Target | Source | Output | Description |
+| :-------------------| :-------------------------------| :----------------------| :----------------------------------------------------|
+| prereqs | | | Install build prerequisites |
+| tools | | cache | Install RISCV compiler and emulator tools, including |
+| | | out/host | Rust, GCC, CLANG, `verilator`, `qemu`, `renode` |
+| kata | kata/ | out/kata | SMC seL4 and user space applications |
+| matcha_tock_release | sw/tock/boards/opentitan-matcha | out/tock-release | The operating system running on the security core, |
+| | sw/libtock-rs | out/libtock-rs | and its Rust library |
+| multihart_boot_rom | sw/multihart_boot_rom | out/shodan_boot_rom | Shodan boot rom |
+| springbok | sw/vec | out/springbok | Vector core BSP and RVV test code |
+| iree_compiler | | out/host/iree_compiler | IREE host compiler |
+| iree_runtime | toolchain/iree | out/springbok_iree | IREE runtime applications |
+| | sw/vec_iree | | |
+| iree | | | Shorthand for `iree_compiler` and `iree_runtime` |
+| opentitan_sw_all | hw/opentitan | out/opentitan | HW testing binaries |
+| qemu | toolchain/ristv-qemu | out/host/qemu | QEMU emulator |
+| renode | sim/renode | out/host/renode | Renode emulator |
+| verilator | sim/verilator | out/host/verilator | System Verilog HW emulator |
+| simulate | | | E2E build and launch renode simulation. |
+| | | | Targets include `matcha_tock_release`, |
+| | | | `kata`, `multihart_boot_rom`, `iree` |
+| debug-simulation | | | Debug version of `simulate` to be used with GDB, |
+| | | | tock target is `matcha_tock_debug`. |
## Clean targets
@@ -38,7 +40,8 @@
| toolchain_clean | Remove cache/toolchain |
| toolchain_llvm_clean | Remove cache/toolchain_iree_rv32imf |
| opentitan_sw_clean | Remove out/opentitan |
-| tock_clean | Clean out/tock (`make clean`) |
+| tock_clean | Clean out/tock-debug |
+| | and out/tock-release (`make clean`) |
## Optional toolchain targets (Used upon request)
diff --git a/GettingStarted.md b/GettingStarted.md
index 9811846..b338297 100644
--- a/GettingStarted.md
+++ b/GettingStarted.md
@@ -310,10 +310,10 @@
and you should see
```bash
-10:41:18.3869 [INFO] uart1: [output] KATA> test_mlexecute
+15:17:59.9864 [INFO] uart1: [output] KATA> test_mlexecute
...
-10:41:18.5931 [INFO] cpu2: simprint: "INFO |simple_vec_mul finished successfully", 0 (0x0)
-10:41:18.5941 [INFO] cpu2: simprint: "main returned: ", 0 (0x0)
+15:18:02.6868 [INFO] cpu2: simprint: "main returned: ", 0 (0x0)
+
```
## More Information
