tx2: Add tx2 reset controller driver

This commit adds a driver for the reset controller in the tx2. Similar
to the clock driver, this driver is mostly just a shim between the BPMP
library as most of the work is carried out by the BPMP co-processor.

libplatsupportports/src/plat/tx2/reset.c

diff --git a/libplatsupportports/src/plat/tx2/reset.c b/libplatsupportports/src/plat/tx2/reset.c
new file mode 100644
index 0000000..ecfaf9a
--- /dev/null
+++ b/libplatsupportports/src/plat/tx2/reset.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright 2020, Data61
+ * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
+ * ABN 41 687 119 230.
+ *
+ * This software may be distributed and modified according to the terms of
+ * the GNU General Public License version 2. Note that NO WARRANTY is provided.
+ * See "LICENSE_GPLv2.txt" for details.
+ *
+ * @TAG(DATA61_GPL)
+ */
+
+#include <errno.h>
+
+#include <platsupport/reset.h>
+#include <platsupport/plat/reset.h>
+
+/* NVIDIA interface */
+#include <tx2bpmp/bpmp.h> /* struct mrq_reset_request */
+
+extern uint32_t mrq_reset_id_map[];
+
+typedef struct tx2_reset {
+    ps_io_ops_t *io_ops;
+    struct tx2_bpmp *bpmp;
+} tx2_reset_t;
+
+static inline bool check_valid_reset(reset_id_t id)
+{
+    return (RESET_TOP_GTE <= id && id < NRESETS);
+}
+
+static int tx2_reset_common(void *data, reset_id_t id, bool assert)
+{
+    if (!check_valid_reset(id)) {
+        ZF_LOGE("Invalid reset ID");
+        return -EINVAL;
+    }
+
+    tx2_reset_t *reset = data;
+    uint32_t bpmp_reset_id = mrq_reset_id_map[id];
+
+    /* Setup a message and make a call to BPMP */
+    struct mrq_reset_request req = { .reset_id = bpmp_reset_id };
+    req.cmd = (assert) ? CMD_RESET_ASSERT : CMD_RESET_DEASSERT;
+
+    int bytes_recvd = tx2_bpmp_call(reset->bpmp, MRQ_RESET, &req, sizeof(req), NULL, 0);
+    if (bytes_recvd < 0) {
+        return -EIO;
+    }
+
+    return 0;
+}
+
+static int tx2_reset_assert(void *data, reset_id_t id)
+{
+    return tx2_reset_common(data, id, true);
+}
+
+static int tx2_reset_deassert(void *data, reset_id_t id)
+{
+    return tx2_reset_common(data, id, false);
+}
+
+int reset_sys_init(ps_io_ops_t *io_ops, void *dependecies, reset_sys_t *reset_sys)
+{
+    if (!io_ops || !reset_sys) {
+        if (!io_ops) {
+            ZF_LOGE("null io_ops argument");
+        }
+
+        if (!reset_sys) {
+            ZF_LOGE("null reset_sys argument");
+        }
+
+        return -EINVAL;
+    }
+
+    int error = 0;
+    bool bpmp_initialised = false;
+    error = ps_calloc(&io_ops->malloc_ops, 1, sizeof(tx2_reset_t), (void **) &reset_sys->data);
+    if (error) {
+        ZF_LOGE("Failed to allocate memory for reset sys internal structure");
+        error = -ENOMEM;
+        goto fail;
+    }
+
+    tx2_reset_t *reset = reset_sys->data;
+
+    error = tx2_bpmp_init(io_ops, &reset->bpmp);
+    if (error) {
+        goto fail;
+    }
+
+    bpmp_initialised = true;
+
+    reset_sys->reset_assert = &tx2_reset_assert;
+    reset_sys->reset_deassert = &tx2_reset_deassert;
+
+    return 0;
+
+fail:
+
+    if (bpmp_initialised) {
+        ZF_LOGF_IF(tx2_bpmp_destroy(io_ops, reset->bpmp),
+                   "Failed to cleanup the BPMP after a failed reset system initialisation");
+    }
+
+    if (reset_sys->data) {
+        ps_free(&io_ops->malloc_ops, sizeof(tx2_reset_t), (void *) reset_sys->data);
+    }
+
+    return error;
+}

libplatsupportports/src/plat/tx2/reset_bindings.c

diff --git a/libplatsupportports/src/plat/tx2/reset_bindings.c b/libplatsupportports/src/plat/tx2/reset_bindings.c
new file mode 100644
index 0000000..ccbeaa4
--- /dev/null
+++ b/libplatsupportports/src/plat/tx2/reset_bindings.c
@@ -0,0 +1,197 @@
+/*
+ * Copright 2020, Data61
+ * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
+ * ABN 41 687 119 230.
+ *
+ * This software may be distributed and modified according to the terms of
+ * the GNU General Public License version 2. Note that NO WARRANTY is provided.
+ * See "LICENSE_GPLv2.txt" for details.
+ *
+ * @TAG(DATA61_GPL)
+ */
+
+#include <stdint.h>
+
+#include <platsupport/plat/reset.h>
+#include <tx2bpmp/reset_bindings.h>
+
+/* This maps the reset_ids to the tx2 BPMP reset IDs */
+
+uint32_t mrq_reset_id_map[] = {
+    [RESET_TOP_GTE] = TEGRA186_RESET_TOP_GTE,
+    [RESET_SHSP] = TEGRA186_RESET_SHSP,
+    [RESET_KFUSE] = TEGRA186_RESET_KFUSE,
+    [RESET_GPU] = TEGRA186_RESET_GPU,
+    [RESET_UPHY] = TEGRA186_RESET_UPHY,
+    [RESET_SPI3] = TEGRA186_RESET_SPI3,
+    [RESET_I2C1] = TEGRA186_RESET_I2C1,
+    [RESET_I2C5] = TEGRA186_RESET_I2C5,
+    [RESET_SPI1] = TEGRA186_RESET_SPI1,
+    [RESET_ISP] = TEGRA186_RESET_ISP,
+    [RESET_VI] = TEGRA186_RESET_VI,
+    [RESET_TSCTNVI] = TEGRA186_RESET_TSCTNVI,
+    [RESET_SDMMC1] = TEGRA186_RESET_SDMMC1,
+    [RESET_SDMMC2] = TEGRA186_RESET_SDMMC2,
+    [RESET_SDMMC3] = TEGRA186_RESET_SDMMC3,
+    [RESET_SDMMC4] = TEGRA186_RESET_SDMMC4,
+    [RESET_UARTA] = TEGRA186_RESET_UARTA,
+    [RESET_UARTB] = TEGRA186_RESET_UARTB,
+    [RESET_HOST1X] = TEGRA186_RESET_HOST1X,
+    [RESET_EXTPERIPH4] = TEGRA186_RESET_EXTPERIPH4,
+    [RESET_SPI4] = TEGRA186_RESET_SPI4,
+    [RESET_I2C3] = TEGRA186_RESET_I2C3,
+    [RESET_UARTD] = TEGRA186_RESET_UARTD,
+    [RESET_CSITE] = TEGRA186_RESET_CSITE,
+    [RESET_DTV] = TEGRA186_RESET_DTV,
+    [RESET_TSEC] = TEGRA186_RESET_TSEC,
+    [RESET_I2C4] = TEGRA186_RESET_I2C4,
+    [RESET_HDA2CODEC_2X] = TEGRA186_RESET_HDA2CODEC_2X,
+    [RESET_EXTPERIPH1] = TEGRA186_RESET_EXTPERIPH1,
+    [RESET_EXTPERIPH2] = TEGRA186_RESET_EXTPERIPH2,
+    [RESET_EXTPERIPH3] = TEGRA186_RESET_EXTPERIPH3,
+    [RESET_SOR0] = TEGRA186_RESET_SOR0,
+    [RESET_SOR1] = TEGRA186_RESET_SOR1,
+    [RESET_DPAUX] = TEGRA186_RESET_DPAUX,
+    [RESET_CEC] = TEGRA186_RESET_CEC,
+    [RESET_HDA] = TEGRA186_RESET_HDA,
+    [RESET_APE] = TEGRA186_RESET_APE,
+    [RESET_DSIPADCTL] = TEGRA186_RESET_DSIPADCTL,
+    [RESET_DSI] = TEGRA186_RESET_DSI,
+    [RESET_MIPI_CAL] = TEGRA186_RESET_MIPI_CAL,
+    [RESET_DVFS] = TEGRA186_RESET_DVFS,
+    [RESET_AUD_MCLK] = TEGRA186_RESET_AUD_MCLK,
+    [RESET_I2C6] = TEGRA186_RESET_I2C6,
+    [RESET_NVDEC] = TEGRA186_RESET_NVDEC,
+    [RESET_NVJPG] = TEGRA186_RESET_NVJPG,
+    [RESET_NVENC] = TEGRA186_RESET_NVENC,
+    [RESET_QSPI] = TEGRA186_RESET_QSPI,
+    [RESET_VI_I2C] = TEGRA186_RESET_VI_I2C,
+    [RESET_TSECB] = TEGRA186_RESET_TSECB,
+    [RESET_GPIO_CTL0] = TEGRA186_RESET_GPIO_CTL0,
+    [RESET_GPIO_CTL1] = TEGRA186_RESET_GPIO_CTL1,
+    [RESET_GPIO_CTL2] = TEGRA186_RESET_GPIO_CTL2,
+    [RESET_GPIO_CTL3] = TEGRA186_RESET_GPIO_CTL3,
+    [RESET_GPIO_CTL4] = TEGRA186_RESET_GPIO_CTL4,
+    [RESET_TACH] = TEGRA186_RESET_TACH,
+    [RESET_I2C7] = TEGRA186_RESET_I2C7,
+    [RESET_I2C9] = TEGRA186_RESET_I2C9,
+    [RESET_I2C12] = TEGRA186_RESET_I2C12,
+    [RESET_I2C13] = TEGRA186_RESET_I2C13,
+    [RESET_I2C14] = TEGRA186_RESET_I2C14,
+    [RESET_PWM1] = TEGRA186_RESET_PWM1,
+    [RESET_PWM2] = TEGRA186_RESET_PWM2,
+    [RESET_PWM3] = TEGRA186_RESET_PWM3,
+    [RESET_PWM5] = TEGRA186_RESET_PWM5,
+    [RESET_PWM6] = TEGRA186_RESET_PWM6,
+    [RESET_PWM7] = TEGRA186_RESET_PWM7,
+    [RESET_PWM8] = TEGRA186_RESET_PWM8,
+    [RESET_UARTE] = TEGRA186_RESET_UARTE,
+    [RESET_UARTF] = TEGRA186_RESET_UARTF,
+    [RESET_BPMP_PM] = TEGRA186_RESET_BPMP_PM,
+    [RESET_BPMP_CVC] = TEGRA186_RESET_BPMP_CVC,
+    [RESET_BPMP_DMA] = TEGRA186_RESET_BPMP_DMA,
+    [RESET_BPMP_HSP] = TEGRA186_RESET_BPMP_HSP,
+    [RESET_TSCTNBPMP] = TEGRA186_RESET_TSCTNBPMP,
+    [RESET_BPMP_TKE] = TEGRA186_RESET_BPMP_TKE,
+    [RESET_BPMP_GTE] = TEGRA186_RESET_BPMP_GTE,
+    [RESET_BPMP_APB] = TEGRA186_RESET_BPMP_APB,
+    [RESET_SOC_THERM] = TEGRA186_RESET_SOC_THERM,
+    [RESET_AON_ACTMON] = TEGRA186_RESET_AON_ACTMON,
+    [RESET_AOPM] = TEGRA186_RESET_AOPM,
+    [RESET_AOVC] = TEGRA186_RESET_AOVC,
+    [RESET_AON_DMA] = TEGRA186_RESET_AON_DMA,
+    [RESET_AON_GPIO] = TEGRA186_RESET_AON_GPIO,
+    [RESET_AON_HSP] = TEGRA186_RESET_AON_HSP,
+    [RESET_CAN1] = TEGRA186_RESET_CAN1,
+    [RESET_AON_APB] = TEGRA186_RESET_AON_APB,
+    [RESET_UARTG] = TEGRA186_RESET_UARTG,
+    [RESET_I2C2] = TEGRA186_RESET_I2C2,
+    [RESET_I2C8] = TEGRA186_RESET_I2C8,
+    [RESET_I2C10] = TEGRA186_RESET_I2C10,
+    [RESET_SPI2] = TEGRA186_RESET_SPI2,
+    [RESET_DMIC5] = TEGRA186_RESET_DMIC5,
+    [RESET_PWM4] = TEGRA186_RESET_PWM4,
+    [RESET_TSCTNAON] = TEGRA186_RESET_TSCTNAON,
+    [RESET_AON_TKE] = TEGRA186_RESET_AON_TKE,
+    [RESET_AON_GTE] = TEGRA186_RESET_AON_GTE,
+    [RESET_SCE_ACTMON] = TEGRA186_RESET_SCE_ACTMON,
+    [RESET_SCE_PM] = TEGRA186_RESET_SCE_PM,
+    [RESET_SCE_DMA] = TEGRA186_RESET_SCE_DMA,
+    [RESET_SCE_HSP] = TEGRA186_RESET_SCE_HSP,
+    [RESET_TSCTNSCE] = TEGRA186_RESET_TSCTNSCE,
+    [RESET_SCE_TKE] = TEGRA186_RESET_SCE_TKE,
+    [RESET_SCE_GTE] = TEGRA186_RESET_SCE_GTE,
+    [RESET_SCE_CFG] = TEGRA186_RESET_SCE_CFG,
+    [RESET_SCE_APB] = TEGRA186_RESET_SCE_APB,
+    [RESET_DSIC] = TEGRA186_RESET_DSIC,
+    [RESET_DSID] = TEGRA186_RESET_DSID,
+    [RESET_GPIO_CTL5] = TEGRA186_RESET_GPIO_CTL5,
+    [RESET_PEX_USB_UPHY_L5] = TEGRA186_RESET_PEX_USB_UPHY_L5,
+    [RESET_PEX_USB_UPHY_L4] = TEGRA186_RESET_PEX_USB_UPHY_L4,
+    [RESET_PEX_USB_UPHY_L3] = TEGRA186_RESET_PEX_USB_UPHY_L3,
+    [RESET_PEX_USB_UPHY_L2] = TEGRA186_RESET_PEX_USB_UPHY_L2,
+    [RESET_PEX_USB_UPHY_L1] = TEGRA186_RESET_PEX_USB_UPHY_L1,
+    [RESET_PEX_USB_UPHY_L0] = TEGRA186_RESET_PEX_USB_UPHY_L0,
+    [RESET_PEX_USB_UPHY_PLL1] = TEGRA186_RESET_PEX_USB_UPHY_PLL1,
+    [RESET_PEX_USB_UPHY_PLL0] = TEGRA186_RESET_PEX_USB_UPHY_PLL0,
+    [RESET_PEX_USB_UPHY] = TEGRA186_RESET_PEX_USB_UPHY,
+    [RESET_PCIEXCLK] = TEGRA186_RESET_PCIEXCLK,
+    [RESET_AFI] = TEGRA186_RESET_AFI,
+    [RESET_PCIE] = TEGRA186_RESET_PCIE,
+    [RESET_ADSPNEON] = TEGRA186_RESET_ADSPNEON,
+    [RESET_ADSPSCU] = TEGRA186_RESET_ADSPSCU,
+    [RESET_ADSPWDT] = TEGRA186_RESET_ADSPWDT,
+    [RESET_ADSPDBG] = TEGRA186_RESET_ADSPDBG,
+    [RESET_ADSPPERIPH] = TEGRA186_RESET_ADSPPERIPH,
+    [RESET_ADSPINTF] = TEGRA186_RESET_ADSPINTF,
+    [RESET_ADSP] = TEGRA186_RESET_ADSP,
+    [RESET_EMC_MEM] = TEGRA186_RESET_EMC_MEM,
+    [RESET_EMC_EMC] = TEGRA186_RESET_EMC_EMC,
+    [RESET_SATACOLD] = TEGRA186_RESET_SATACOLD,
+    [RESET_SATA] = TEGRA186_RESET_SATA,
+    [RESET_XUSB_SS] = TEGRA186_RESET_XUSB_SS,
+    [RESET_XUSB_PADCTL] = TEGRA186_RESET_XUSB_PADCTL,
+    [RESET_XUSB_DEV] = TEGRA186_RESET_XUSB_DEV,
+    [RESET_XUSB_HOST] = TEGRA186_RESET_XUSB_HOST,
+    [RESET_DSIB] = TEGRA186_RESET_DSIB,
+    [RESET_MPHY_IOBIST] = TEGRA186_RESET_MPHY_IOBIST,
+    [RESET_MPHY_CLK_CTL] = TEGRA186_RESET_MPHY_CLK_CTL,
+    [RESET_MPHY_L1_RX] = TEGRA186_RESET_MPHY_L1_RX,
+    [RESET_MPHY_L1_TX] = TEGRA186_RESET_MPHY_L1_TX,
+    [RESET_MPHY_L0_RX] = TEGRA186_RESET_MPHY_L0_RX,
+    [RESET_MPHY_L0_TX] = TEGRA186_RESET_MPHY_L0_TX,
+    [RESET_JTAG2AXI] = TEGRA186_RESET_JTAG2AXI,
+    [RESET_GPCDMA] = TEGRA186_RESET_GPCDMA,
+    [RESET_NVDISPLAY0_MISC] = TEGRA186_RESET_NVDISPLAY0_MISC,
+    [RESET_NVDISPLAY0_WGRP5] = TEGRA186_RESET_NVDISPLAY0_WGRP5,
+    [RESET_NVDISPLAY0_WGRP4] = TEGRA186_RESET_NVDISPLAY0_WGRP4,
+    [RESET_NVDISPLAY0_WGRP3] = TEGRA186_RESET_NVDISPLAY0_WGRP3,
+    [RESET_NVDISPLAY0_WGRP2] = TEGRA186_RESET_NVDISPLAY0_WGRP2,
+    [RESET_NVDISPLAY0_WGRP1] = TEGRA186_RESET_NVDISPLAY0_WGRP1,
+    [RESET_NVDISPLAY0_WGRP0] = TEGRA186_RESET_NVDISPLAY0_WGRP0,
+    [RESET_NVDISPLAY0_HEAD2] = TEGRA186_RESET_NVDISPLAY0_HEAD2,
+    [RESET_NVDISPLAY0_HEAD1] = TEGRA186_RESET_NVDISPLAY0_HEAD1,
+    [RESET_NVDISPLAY0_HEAD0] = TEGRA186_RESET_NVDISPLAY0_HEAD0,
+    [RESET_EMCSB_MEM] = TEGRA186_RESET_EMCSB_MEM,
+    [RESET_EMCSB_EMC] = TEGRA186_RESET_EMCSB_EMC,
+    [RESET_UFSHC_AXI_M] = TEGRA186_RESET_UFSHC_AXI_M,
+    [RESET_UFSHC_LP] = TEGRA186_RESET_UFSHC_LP,
+    [RESET_BPMP_NIC] = TEGRA186_RESET_BPMP_NIC,
+    [RESET_BPMP_NSYSPORESET] = TEGRA186_RESET_BPMP_NSYSPORESET,
+    [RESET_BPMP_NRESET] = TEGRA186_RESET_BPMP_NRESET,
+    [RESET_BPMP_DBGRESETN] = TEGRA186_RESET_BPMP_DBGRESETN,
+    [RESET_BPMP_PRESETDBGN] = TEGRA186_RESET_BPMP_PRESETDBGN,
+    [RESET_BPMP_PM_ACTMON] = TEGRA186_RESET_BPMP_PM_ACTMON,
+    [RESET_ACTMON] = TEGRA186_RESET_ACTMON,
+    [RESET_AON_NIC] = TEGRA186_RESET_AON_NIC,
+    [RESET_AON_NSYSPORESET] = TEGRA186_RESET_AON_NSYSPORESET,
+    [RESET_AON_NRESET] = TEGRA186_RESET_AON_NRESET,
+    [RESET_AON_DBGRESETN] = TEGRA186_RESET_AON_DBGRESETN,
+    [RESET_AON_PRESETDBGN] = TEGRA186_RESET_AON_PRESETDBGN,
+    [RESET_SCE_NIC] = TEGRA186_RESET_SCE_NIC,
+    [RESET_SCE_NSYSPORESET] = TEGRA186_RESET_SCE_NSYSPORESET,
+    [RESET_SCE_NRESET] = TEGRA186_RESET_SCE_NRESET,
+    [RESET_SCE_DBGRESETN] = TEGRA186_RESET_SCE_DBGRESETN,
+    [RESET_SCE_PRESETDBGN] = TEGRA186_RESET_SCE_PRESETDBGN,
+    [RESET_EQOS] = TEGRA186_RESET_EQOS,
+};

libtx2bpmp/include/tx2bpmp/reset_bindings.h

diff --git a/libtx2bpmp/include/tx2bpmp/reset_bindings.h b/libtx2bpmp/include/tx2bpmp/reset_bindings.h
new file mode 100644
index 0000000..6c14d70
--- /dev/null
+++ b/libtx2bpmp/include/tx2bpmp/reset_bindings.h
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION.
+ *
+ * This software may be distributed and modified according to the terms of
+ * the GNU General Public License version 2. Note that NO WARRANTY is provided.
+ * See "LICENSE_GPLv2.txt" for details.
+ *
+ * @TAG(OTHER_GPL)
+ */
+
+#pragma once
+
+
+#define TEGRA186_RESET_ACTMON           0
+#define TEGRA186_RESET_AFI          1
+#define TEGRA186_RESET_CEC          2
+#define TEGRA186_RESET_CSITE            3
+#define TEGRA186_RESET_DP2          4
+#define TEGRA186_RESET_DPAUX            5
+#define TEGRA186_RESET_DSI          6
+#define TEGRA186_RESET_DSIB         7
+#define TEGRA186_RESET_DTV          8
+#define TEGRA186_RESET_DVFS         9
+#define TEGRA186_RESET_ENTROPY          10
+#define TEGRA186_RESET_EXTPERIPH1       11
+#define TEGRA186_RESET_EXTPERIPH2       12
+#define TEGRA186_RESET_EXTPERIPH3       13
+#define TEGRA186_RESET_GPU          14
+#define TEGRA186_RESET_HDA          15
+#define TEGRA186_RESET_HDA2CODEC_2X     16
+#define TEGRA186_RESET_HDA2HDMICODEC        17
+#define TEGRA186_RESET_HOST1X           18
+#define TEGRA186_RESET_I2C1         19
+#define TEGRA186_RESET_I2C2         20
+#define TEGRA186_RESET_I2C3         21
+#define TEGRA186_RESET_I2C4         22
+#define TEGRA186_RESET_I2C5         23
+#define TEGRA186_RESET_I2C6         24
+#define TEGRA186_RESET_ISP          25
+#define TEGRA186_RESET_KFUSE            26
+#define TEGRA186_RESET_LA           27
+#define TEGRA186_RESET_MIPI_CAL         28
+#define TEGRA186_RESET_PCIE         29
+#define TEGRA186_RESET_PCIEXCLK         30
+#define TEGRA186_RESET_SATA         31
+#define TEGRA186_RESET_SATACOLD         32
+#define TEGRA186_RESET_SDMMC1           33
+#define TEGRA186_RESET_SDMMC2           34
+#define TEGRA186_RESET_SDMMC3           35
+#define TEGRA186_RESET_SDMMC4           36
+#define TEGRA186_RESET_SE           37
+#define TEGRA186_RESET_SOC_THERM        38
+#define TEGRA186_RESET_SOR0         39
+#define TEGRA186_RESET_SPI1         40
+#define TEGRA186_RESET_SPI2         41
+#define TEGRA186_RESET_SPI3         42
+#define TEGRA186_RESET_SPI4         43
+#define TEGRA186_RESET_TMR          44
+#define TEGRA186_RESET_TRIG_SYS         45
+#define TEGRA186_RESET_TSEC         46
+#define TEGRA186_RESET_UARTA            47
+#define TEGRA186_RESET_UARTB            48
+#define TEGRA186_RESET_UARTC            49
+#define TEGRA186_RESET_UARTD            50
+#define TEGRA186_RESET_VI           51
+#define TEGRA186_RESET_VIC          52
+#define TEGRA186_RESET_XUSB_DEV         53
+#define TEGRA186_RESET_XUSB_HOST        54
+#define TEGRA186_RESET_XUSB_PADCTL      55
+#define TEGRA186_RESET_XUSB_SS          56
+#define TEGRA186_RESET_AON_APB          57
+#define TEGRA186_RESET_AXI_CBB          58
+#define TEGRA186_RESET_BPMP_APB         59
+#define TEGRA186_RESET_CAN1         60
+#define TEGRA186_RESET_CAN2         61
+#define TEGRA186_RESET_DMIC5            62
+#define TEGRA186_RESET_DSIC         63
+#define TEGRA186_RESET_DSID         64
+#define TEGRA186_RESET_EMC_EMC          65
+#define TEGRA186_RESET_EMC_MEM          66
+#define TEGRA186_RESET_EMCSB_EMC        67
+#define TEGRA186_RESET_EMCSB_MEM        68
+#define TEGRA186_RESET_EQOS         69
+#define TEGRA186_RESET_GPCDMA           70
+#define TEGRA186_RESET_GPIO_CTL0        71
+#define TEGRA186_RESET_GPIO_CTL1        72
+#define TEGRA186_RESET_GPIO_CTL2        73
+#define TEGRA186_RESET_GPIO_CTL3        74
+#define TEGRA186_RESET_GPIO_CTL4        75
+#define TEGRA186_RESET_GPIO_CTL5        76
+#define TEGRA186_RESET_I2C10            77
+#define TEGRA186_RESET_I2C12            78
+#define TEGRA186_RESET_I2C13            79
+#define TEGRA186_RESET_I2C14            80
+#define TEGRA186_RESET_I2C7         81
+#define TEGRA186_RESET_I2C8         82
+#define TEGRA186_RESET_I2C9         83
+#define TEGRA186_RESET_JTAG2AXI         84
+#define TEGRA186_RESET_MPHY_IOBIST      85
+#define TEGRA186_RESET_MPHY_L0_RX       86
+#define TEGRA186_RESET_MPHY_L0_TX       87
+#define TEGRA186_RESET_NVCSI            88
+#define TEGRA186_RESET_NVDISPLAY0_HEAD0     89
+#define TEGRA186_RESET_NVDISPLAY0_HEAD1     90
+#define TEGRA186_RESET_NVDISPLAY0_HEAD2     91
+#define TEGRA186_RESET_NVDISPLAY0_MISC      92
+#define TEGRA186_RESET_NVDISPLAY0_WGRP0     93
+#define TEGRA186_RESET_NVDISPLAY0_WGRP1     94
+#define TEGRA186_RESET_NVDISPLAY0_WGRP2     95
+#define TEGRA186_RESET_NVDISPLAY0_WGRP3     96
+#define TEGRA186_RESET_NVDISPLAY0_WGRP4     97
+#define TEGRA186_RESET_NVDISPLAY0_WGRP5     98
+#define TEGRA186_RESET_PWM1         99
+#define TEGRA186_RESET_PWM2         100
+#define TEGRA186_RESET_PWM3         101
+#define TEGRA186_RESET_PWM4         102
+#define TEGRA186_RESET_PWM5         103
+#define TEGRA186_RESET_PWM6         104
+#define TEGRA186_RESET_PWM7         105
+#define TEGRA186_RESET_PWM8         106
+#define TEGRA186_RESET_SCE_APB          107
+#define TEGRA186_RESET_SOR1         108
+#define TEGRA186_RESET_TACH         109
+#define TEGRA186_RESET_TSC          110
+#define TEGRA186_RESET_UARTF            111
+#define TEGRA186_RESET_UARTG            112
+#define TEGRA186_RESET_UFSHC            113
+#define TEGRA186_RESET_UFSHC_AXI_M      114
+#define TEGRA186_RESET_UPHY         115
+#define TEGRA186_RESET_ADSP         116
+#define TEGRA186_RESET_ADSPDBG          117
+#define TEGRA186_RESET_ADSPINTF         118
+#define TEGRA186_RESET_ADSPNEON         119
+#define TEGRA186_RESET_ADSPPERIPH       120
+#define TEGRA186_RESET_ADSPSCU          121
+#define TEGRA186_RESET_ADSPWDT          122
+#define TEGRA186_RESET_APE          123
+#define TEGRA186_RESET_DPAUX1           124
+#define TEGRA186_RESET_NVDEC            125
+#define TEGRA186_RESET_NVENC            126
+#define TEGRA186_RESET_NVJPG            127
+#define TEGRA186_RESET_PEX_USB_UPHY     128
+#define TEGRA186_RESET_QSPI         129
+#define TEGRA186_RESET_TSECB            130
+#define TEGRA186_RESET_VI_I2C           131
+#define TEGRA186_RESET_UARTE            132
+#define TEGRA186_RESET_TOP_GTE          133
+#define TEGRA186_RESET_SHSP         134
+#define TEGRA186_RESET_PEX_USB_UPHY_L5      135
+#define TEGRA186_RESET_PEX_USB_UPHY_L4      136
+#define TEGRA186_RESET_PEX_USB_UPHY_L3      137
+#define TEGRA186_RESET_PEX_USB_UPHY_L2      138
+#define TEGRA186_RESET_PEX_USB_UPHY_L1      139
+#define TEGRA186_RESET_PEX_USB_UPHY_L0      140
+#define TEGRA186_RESET_PEX_USB_UPHY_PLL1    141
+#define TEGRA186_RESET_PEX_USB_UPHY_PLL0    142
+#define TEGRA186_RESET_TSCTNVI          143
+#define TEGRA186_RESET_EXTPERIPH4       144
+#define TEGRA186_RESET_DSIPADCTL        145
+#define TEGRA186_RESET_AUD_MCLK         146
+#define TEGRA186_RESET_MPHY_CLK_CTL     147
+#define TEGRA186_RESET_MPHY_L1_RX       148
+#define TEGRA186_RESET_MPHY_L1_TX       149
+#define TEGRA186_RESET_UFSHC_LP         150
+#define TEGRA186_RESET_BPMP_NIC         151
+#define TEGRA186_RESET_BPMP_NSYSPORESET     152
+#define TEGRA186_RESET_BPMP_NRESET      153
+#define TEGRA186_RESET_BPMP_DBGRESETN       154
+#define TEGRA186_RESET_BPMP_PRESETDBGN      155
+#define TEGRA186_RESET_BPMP_PM          156
+#define TEGRA186_RESET_BPMP_CVC         157
+#define TEGRA186_RESET_BPMP_DMA         158
+#define TEGRA186_RESET_BPMP_HSP         159
+#define TEGRA186_RESET_TSCTNBPMP        160
+#define TEGRA186_RESET_BPMP_TKE         161
+#define TEGRA186_RESET_BPMP_GTE         162
+#define TEGRA186_RESET_BPMP_PM_ACTMON       163
+#define TEGRA186_RESET_AON_NIC          164
+#define TEGRA186_RESET_AON_NSYSPORESET      165
+#define TEGRA186_RESET_AON_NRESET       166
+#define TEGRA186_RESET_AON_DBGRESETN        167
+#define TEGRA186_RESET_AON_PRESETDBGN       168
+#define TEGRA186_RESET_AON_ACTMON       169
+#define TEGRA186_RESET_AOPM         170
+#define TEGRA186_RESET_AOVC         171
+#define TEGRA186_RESET_AON_DMA          172
+#define TEGRA186_RESET_AON_GPIO         173
+#define TEGRA186_RESET_AON_HSP          174
+#define TEGRA186_RESET_TSCTNAON         175
+#define TEGRA186_RESET_AON_TKE          176
+#define TEGRA186_RESET_AON_GTE          177
+#define TEGRA186_RESET_SCE_NIC          178
+#define TEGRA186_RESET_SCE_NSYSPORESET      179
+#define TEGRA186_RESET_SCE_NRESET       180
+#define TEGRA186_RESET_SCE_DBGRESETN        181
+#define TEGRA186_RESET_SCE_PRESETDBGN       182
+#define TEGRA186_RESET_SCE_ACTMON       183
+#define TEGRA186_RESET_SCE_PM           184
+#define TEGRA186_RESET_SCE_DMA          185
+#define TEGRA186_RESET_SCE_HSP          186
+#define TEGRA186_RESET_TSCTNSCE         187
+#define TEGRA186_RESET_SCE_TKE          188
+#define TEGRA186_RESET_SCE_GTE          189
+#define TEGRA186_RESET_SCE_CFG          190
+#define TEGRA186_RESET_ADSP_ALL         191
+/** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */
+#define TEGRA186_RESET_UFSHC_LP_SEQ     192
+#define TEGRA186_RESET_SIZE         193