libethdrivers/src/plat/imx6/uboot/mx6qsabrelite.h

/*
 * @TAG(OTHER_GPL)
 */

/*
 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
 *
 * Configuration settings for the Freescale i.MX6Q Sabre Lite board.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.     See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#pragma once

#define CONFIG_MX6
#define CONFIG_MX6Q

#define CONFIG_MACH_TYPE    3769

#include "imx-regs.h"
#include "gpio.h"

#include <stdint.h>

#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
#define CONFIG_MXC_GPIO

#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE            ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE     RGMII
#define CONFIG_ETHPRIME         "FEC"
#define CONFIG_FEC_MXC_PHYMASK      (0xf << 4)  /* scan phy 4,5,6,7 */
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021

/* Command definition */
#include "config.h"

#define CONFIG_MX6
#define CONFIG_MX6Q

#include "imx-regs.h"

#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MXC_GPIO

#define CONFIG_MXC_UART
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE            ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE     RGMII
#define CONFIG_ETHPRIME         "FEC"
#define CONFIG_FEC_MXC_PHYADDR      1

#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS

/* Command definition */
#include "config.h"
typedef uint64_t iomux_v3_cfg_t;

#define MUX_CTRL_OFS_SHIFT  0
#define MUX_CTRL_OFS_MASK   ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
#define MUX_PAD_CTRL_OFS_SHIFT  12
#define MUX_PAD_CTRL_OFS_MASK   ((iomux_v3_cfg_t)0xfff << \
    MUX_PAD_CTRL_OFS_SHIFT)
#define MUX_SEL_INPUT_OFS_SHIFT 24
#define MUX_SEL_INPUT_OFS_MASK  ((iomux_v3_cfg_t)0xfff << \
    MUX_SEL_INPUT_OFS_SHIFT)

#define MUX_MODE_SHIFT      36
#define MUX_MODE_MASK       ((iomux_v3_cfg_t)0x3f << MUX_MODE_SHIFT)
#define MUX_PAD_CTRL_SHIFT  42
#define MUX_PAD_CTRL_MASK   ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
#define MUX_SEL_INPUT_SHIFT 60
#define MUX_SEL_INPUT_MASK  ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)

#define MUX_PAD_CTRL(x)     ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)

#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs,  \
        sel_input, pad_ctrl)                    \
    (((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT)     |   \
    ((iomux_v3_cfg_t)(mux_mode)      << MUX_MODE_SHIFT)         |   \
    ((iomux_v3_cfg_t)(pad_ctrl_ofs)  << MUX_PAD_CTRL_OFS_SHIFT) |   \
    ((iomux_v3_cfg_t)(pad_ctrl)      << MUX_PAD_CTRL_SHIFT)     |   \
    ((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)|   \
    ((iomux_v3_cfg_t)(sel_input)     << MUX_SEL_INPUT_SHIFT))

#define NO_PAD_CTRL     (BIT(17))
#define GPIO_PIN_MASK       0x1f
#define GPIO_PORT_SHIFT     5
#define GPIO_PORT_MASK      (0x7 << GPIO_PORT_SHIFT)
#define GPIO_PORTA      (0 << GPIO_PORT_SHIFT)
#define GPIO_PORTB      (BIT(GPIO_PORT_SHIFT))
#define GPIO_PORTC      (2 << GPIO_PORT_SHIFT)
#define GPIO_PORTD      (3 << GPIO_PORT_SHIFT)
#define GPIO_PORTE      (4 << GPIO_PORT_SHIFT)
#define GPIO_PORTF      (5 << GPIO_PORT_SHIFT)

#define MUX_CONFIG_SION     (BIT(4))