| /* |
| * Copyright 2014, NICTA |
| * |
| * This software may be distributed and modified according to the terms of |
| * the BSD 2-Clause license. Note that NO WARRANTY is provided. |
| * See "LICENSE_BSD2.txt" for details. |
| * |
| * @TAG(NICTA_BSD) |
| */ |
| |
| //PMC event definitions |
| /* Note: there are lots of these. Only seemingly interesting ones -- that is, |
| * either core sel4bench events, or ones closely related -- are included here. |
| * Note2: events numbers are 16 bits long, and are divided into an ID (lower |
| * byte) and a mask (upper byte). Events with the same ID but differing masks |
| * can usually be ORed together, in which case they'll be counted together. |
| */ |
| |
| //Arch |
| #define SEL4BENCH_IA32_EVENT_CYCLE_CORE 0x003C |
| #define SEL4BENCH_IA32_EVENT_CYCLE_BUS 0x013C |
| #define SEL4BENCH_IA32_EVENT_CACHE_LLC_ACCESS 0x4F2E |
| #define SEL4BENCH_IA32_EVENT_CACHE_LLC_MISS 0x412E |
| #define SEL4BENCH_IA32_EVENT_EXECUTE_INSTRUCTION 0x00C0 |
| #define SEL4BENCH_IA32_EVENT_EXECUTE_BRANCH 0x00C4 |
| #define SEL4BENCH_IA32_EVENT_BRANCH_MISPREDICT 0x00C5 |
| //event modifiers |
| #define SEL4BENCH_IA32_MESI(X, EVENT) ((EVENT) | ((X) << 8)) |
| #define SEL4BENCH_IA32_CORE(X, EVENT) ((EVENT) | ((X) << 14)) |
| #define SEL4BENCH_IA32_PREFETCH(X, EVENT) ((EVENT) | ((X) << 12)) |
| #define SEL4BENCH_IA32_CORE_SELF 0x1 |
| #define SEL4BENCH_IA32_CORE_ALL 0x3 |
| #define SEL4BENCH_IA32_PREFETCH_NONE 0x0 |
| #define SEL4BENCH_IA32_PREFETCH_ONLY 0x1 |
| #define SEL4BENCH_IA32_PREFETCH_ALL 0x3 |
| #define SEL4BENCH_IA32_M BIT(3) |
| #define SEL4BENCH_IA32_E BIT(2) |
| #define SEL4BENCH_IA32_S BIT(1) |
| #define SEL4BENCH_IA32_I BIT(0) |
| #define SEL4BENCH_IA32_CACHEMISS SEL4BENCH_IA32_I |
| #define SEL4BENCH_IA32_CACHEHIT (SEL4BENCH_IA32_M | SEL4BENCH_IA32_E | SEL4BENCH_IA32_S) |
| |
| //Westmere uArch |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_TLB_DMISS_READ 0x0208 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_TLB_DHIT_READ 0x1008 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_READ_HIT 0x0124 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_READ_MISS 0x0224 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_WRITE_HIT 0x0424 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_WRITE_MISS 0x0824 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_IFETCH_HIT 0x1024 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_IFETCH_MISS 0x2024 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_PFETCH_HIT 0x4024 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_PFETCH_MISS 0x8024 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_ACCESS 0x0026 //modifiers: MESI (demand), MESI << 4 (prefetch) |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_WRITE 0x0027 //modifiers: MESI ( RFO), MESI << 4 ( lock) |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L3_MISS 0x012E |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L3_ACCESS 0x022E |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_TLB_DMISS 0x0249 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L1D_LINES_IN 0x0151 //must use counter 0 or 1 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L1I_HIT 0x0180 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L1I_MISS 0x0280 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_TLB_IHIT_LARGEPAGE 0x0182 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_TLB_IMISS 0x0285 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_EXECUTE_BRANCH 0x7F88 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_BRANCH_MISPREDICT 0x7F89 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_TLB_IFLUSH 0x01AE |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_RETIRE_INSTRUCTION 0x00C0 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_SELF_MODIFYING_CODE 0x04C3 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_RETIRE_BRANCH 0x00C4 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_BRANCH_MISPREDICT_R 0x00C5 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_TLB_IMISS_R 0x20C8 |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L1D_HIT_R 0x01CB |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_HIT_R 0x02CB |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L3P_HIT_R 0x04CB |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L3_HIT_R 0x08CB |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L3_MISS_R 0x10CB |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_LFB_HIT_R 0x40CB |
| #define SEL4BENCH_IA32_WESTMERE_EVENT_TLB_DMISS_R 0x80CB |
| |
| //Nehalem uArch |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_TLB_DMISS_READ 0x0208 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_TLB_DHIT_READ 0x1008 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_READ_HIT 0x0124 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_READ_MISS 0x0224 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_WRITE_HIT 0x0424 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_WRITE_MISS 0x0824 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_IFETCH_HIT 0x1024 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_IFETCH_MISS 0x2024 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_PFETCH_HIT 0x4024 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_PFETCH_MISS 0x8024 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_ACCESS 0x0026 //modifiers: MESI (demand), MESI << 4 (prefetch) |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_WRITE 0x0027 //modifiers: MESI ( RFO), MESI << 4 ( lock) |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L3_MISS 0x412E |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L3_ACCESS 0x4F2E |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L1D_READ 0x0040 //modifiers: MESI; must use counter 0 or 1 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L1D_WRITE 0x0041 //modifiers: MESI; must use counter 0 or 1 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L1D_READ_LOCK 0x0042 //modifiers: MESI; must use counter 0 or 1 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L1D_ACCESS 0x0143 //must use counter 0 or 1 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L1D_ACCESS_C 0x0243 //must use counter 0 or 1 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_TLB_DMISS 0x0249 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L1D_LINES_IN 0x0151 //must use counter 0 or 1 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L1I_HIT 0x0180 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L1I_MISS 0x0280 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_TLB_IHIT_LARGEPAGE 0x0182 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_TLB_IMISS 0x0285 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_EXECUTE_BRANCH 0x7F88 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_BRANCH_MISPREDICT 0x7F89 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_TLB_IFLUSH 0x01AE |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_RETIRE_INSTRUCTION 0x00C0 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_SELF_MODIFYING_CODE 0x04C3 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_RETIRE_BRANCH 0x00C4 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_BRANCH_MISPREDICT_R 0x00C5 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_TLB_IMISS_R 0x20C8 |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L1D_HIT_R 0x01CB |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_HIT_R 0x02CB |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L3P_HIT_R 0x04CB |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L3_HIT_R 0x08CB |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L3_MISS_R 0x10CB |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_LFB_HIT_R 0x40CB |
| #define SEL4BENCH_IA32_NEHALEM_EVENT_TLB_DMISS_R 0x80CB |
| |
| //Core2 series (aka Core uArch) |
| //events are subject to modifiers above, as commented |
| #define SEL4BENCH_IA32_CORE2_EVENT_SEGMENT_LOAD 0x0006 |
| #define SEL4BENCH_IA32_CORE2_EVENT_TLB_DMISS 0x0108 |
| #define SEL4BENCH_IA32_CORE2_EVENT_TLB_DMISS_READ 0x0208 |
| #define SEL4BENCH_IA32_CORE2_EVENT_TLB_L0D_MISS_READ 0x0408 |
| #define SEL4BENCH_IA32_CORE2_EVENT_TLB_DMISS_WRITE 0x0808 |
| #define SEL4BENCH_IA32_CORE2_EVENT_PAGETABLE_WALK 0x010C |
| #define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L2_MISS 0x0024 //modifiers: CORE, PREFETCH |
| #define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L2_EVICT 0x0026 //modifiers: CORE, PREFETCH |
| #define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L2_IFETCH 0x0028 //modifiers: CORE, MESI |
| #define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L2_READ 0x0029 //modifiers: CORE, PREFETCH, MESI |
| #define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L2_WRITE 0x002A //modifiers: CORE, MESI |
| #define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L2_LOCK 0x002B //modifiers: CORE, MESI |
| #define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L2_ACCESS 0x002E //modifiers: CORE, PREFETCH, MESI |
| #define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1D_READ 0x0040 //modifiers: MESI |
| #define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1D_WRITE 0x0041 //modifiers: MESI |
| #define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1D_READ_LOCK 0x0042 //modifiers: MESI |
| #define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1D_ACCESS 0x0143 |
| #define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1D_ACCESS_C 0x0243 |
| #define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1D_READ_SPLIT 0x0149 |
| #define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1D_WRITE_SPLIT 0x0249 |
| #define SEL4BENCH_IA32_CORE2_EVENT_INSTRUCTION_FETCH 0x0080 |
| #define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1I_MISS 0x0081 |
| #define SEL4BENCH_IA32_CORE2_EVENT_TLB_IMISS_SMALLPAGE 0x0282 |
| #define SEL4BENCH_IA32_CORE2_EVENT_TLB_IMISS_LARGEPAGE 0x1082 |
| #define SEL4BENCH_IA32_CORE2_EVENT_TLB_IFLUSH 0x4082 |
| #define SEL4BENCH_IA32_CORE2_EVENT_TLB_IMISS 0x1282 |
| #define SEL4BENCH_IA32_CORE2_EVENT_EXECUTE_BRANCH 0x0088 |
| #define SEL4BENCH_IA32_CORE2_EVENT_BRANCH_MISPREDICT 0x0089 |
| #define SEL4BENCH_IA32_CORE2_EVENT_RETIRE_INSTRUCTION 0x00C0 |
| #define SEL4BENCH_IA32_CORE2_EVENT_RETIRE_MEMORY_READ 0x01C0 |
| #define SEL4BENCH_IA32_CORE2_EVENT_RETIRE_MEMORY_WRITE 0x02C0 |
| #define SEL4BENCH_IA32_CORE2_EVENT_RETIRE_NONMEMORY 0x04C0 |
| #define SEL4BENCH_IA32_CORE2_EVENT_SELF_MODIFYING_CODE 0x01C3 |
| #define SEL4BENCH_IA32_CORE2_EVENT_RETIRE_BRANCH 0x00C4 |
| #define SEL4BENCH_IA32_CORE2_EVENT_BRANCH_MISPREDICT_R 0x00C5 |
| #define SEL4BENCH_IA32_CORE2_EVENT_HARDWARE_INTERRUPT 0x00C8 |
| #define SEL4BENCH_IA32_CORE2_EVENT_TLB_IMISS_R 0x00C9 |
| #define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1D_MISS_R 0x01CB //must use counter 0 |
| #define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1D_MISS_LINE_R 0x02CB //must use counter 0 |
| #define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L2_MISS_R 0x04CB //must use counter 0 |
| #define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L2_MISS_LINE_R 0x08CB //must use counter 0 |
| #define SEL4BENCH_IA32_CORE2_EVENT_TLB_DMISS_R 0x10CB //must use counter 0 |
| |
| //Core Solo / Core Duo processors |
| //events are subject to modifiers above, as commented |
| #define SEL4BENCH_IA32_CORE_EVENT_SEGMENT_LOAD 0x0006 |
| #define SEL4BENCH_IA32_CORE_EVENT_CACHE_L2_ALLOC 0x0024 |
| #define SEL4BENCH_IA32_CORE_EVENT_CACHE_L2_ALLOC_DIRTY 0x0025 |
| #define SEL4BENCH_IA32_CORE_EVENT_CACHE_L2_EVICT 0x0026 |
| #define SEL4BENCH_IA32_CORE_EVENT_CACHE_L2_EVICT_DIRTY 0x0027 |
| #define SEL4BENCH_IA32_CORE_EVENT_CACHE_L2_IFETCH 0x0028 //modifiers: MESI |
| #define SEL4BENCH_IA32_CORE_EVENT_CACHE_L2_READ 0x0029 //modifiers: MESI |
| #define SEL4BENCH_IA32_CORE_EVENT_CACHE_L2_WRITE 0x002A //modifiers: MESI |
| #define SEL4BENCH_IA32_CORE_EVENT_CACHE_L2_ACCESS 0x002E //modifiers: MESI |
| #define SEL4BENCH_IA32_CORE_EVENT_CACHE_L1D_READ 0x0040 //modifiers: MESI |
| #define SEL4BENCH_IA32_CORE_EVENT_CACHE_L1D_WRITE 0x0041 //modifiers: MESI |
| #define SEL4BENCH_IA32_CORE_EVENT_CACHE_L1D_READ_LOCK 0x0042 //modifiers: MESI |
| #define SEL4BENCH_IA32_CORE_EVENT_CACHE_L1D_ACCESS 0x0143 |
| #define SEL4BENCH_IA32_CORE_EVENT_CACHE_L1D_ACCESS_C 0x0243 |
| #define SEL4BENCH_IA32_CORE_EVENT_CACHED_MEMORY_ACCESS 0x0244 |
| #define SEL4BENCH_IA32_CORE_EVENT_CACHE_L1D_EVICT 0x0F45 |
| #define SEL4BENCH_IA32_CORE_EVENT_CACHE_L1D_ALLOC_DIRTY 0x0046 |
| #define SEL4BENCH_IA32_CORE_EVENT_CACHE_L1D_EVICT_DIRTY 0x0047 |
| #define SEL4BENCH_IA32_CORE_EVENT_TLB_DMISS 0x0049 |
| #define SEL4BENCH_IA32_CORE_EVENT_INSTRUCTION_FETCH 0x0080 |
| #define SEL4BENCH_IA32_CORE_EVENT_CACHE_L1I_MISS 0x0081 |
| #define SEL4BENCH_IA32_CORE_EVENT_TLB_IMISS 0x0085 |
| #define SEL4BENCH_IA32_CORE_EVENT_EXECUTE_BRANCH 0x0088 |
| #define SEL4BENCH_IA32_CORE_EVENT_BRANCH_MISPREDICT 0x0089 |
| #define SEL4BENCH_IA32_CORE_EVENT_RETIRE_INSTRUCTION 0x00C0 |
| #define SEL4BENCH_IA32_CORE_EVENT_SELF_MODIFYING_CODE 0x00C3 |
| #define SEL4BENCH_IA32_CORE_EVENT_RETIRE_BRANCH 0x00C4 |
| #define SEL4BENCH_IA32_CORE_EVENT_BRANCH_MISPREDICT_R 0x00C5 |
| #define SEL4BENCH_IA32_CORE_EVENT_HARDWARE_INTERRUPT 0x00C8 |
| #define SEL4BENCH_IA32_CORE_EVENT_RETIRE_BRANCH_TRUE 0x00C9 |
| #define SEL4BENCH_IA32_CORE_EVENT_BRANCH_MISPREDICT_TRUE_R 0x00C5 |
| #define SEL4BENCH_IA32_CORE_EVENT_BTB_MISS 0x00E2 |
| |
| //Haswell uArch |
| #define SEL4BENCH_IA32_HASWELL_EVENT_CACHE_L1I_MISS 0x0081 |
| #define SEL4BENCH_IA32_HASWELL_EVENT_CACHE_L1D_REPLACEMENT 0x0151 |
| #define SEL4BENCH_IA32_HASWELL_EVENT_CACHE_L2_MISS 0x3F24 |
| #define SEL4BENCH_IA32_HASWELL_EVENT_TX_MEM_ABORT_CONFLICT 0x0154 |
| #define SEL4BENCH_IA32_HASWELL_EVENT_TX_MEM_ABORT_CAPACITY_WRITE 0x0154 |
| /* Counts the number of times a class of instructions that may cause a |
| transactional abort was executed. Since this is the count of execution, |
| it may not always cause a transactional abort. */ |
| #define SEL4BENCH_IA32_HASWELL_EVENT_TX_EXEC_MISC1 0x015D |
| /* Counts the number of times a class of instructions (e.g. vzeroupper) that |
| may cause a transactional abort was executed inside a transactional region */ |
| #define SEL4BENCH_IA32_HASWELL_EVENT_TX_EXEC_MISC2 0x025D |
| #define SEL4BENCH_IA32_HASWELL_EVENT_TX_EXEC_NEST_EXCEEDED 0x045D |
| #define SEL4BENCH_IA32_HASWELL_EVENT_RTM_RETIRED_START 0x01C9 |
| #define SEL4BENCH_IA32_HASWELL_EVENT_RTM_RETIRED_COMMIT 0x02C9 |
| #define SEL4BENCH_IA32_HASWELL_EVENT_RTM_RETIRED_ABORTED 0x04C9 |
| #define SEL4BENCH_IA32_HASWELL_EVENT_RTM_RETIRED_ABORTED_MEM_EVENT 0x08C9 |
| #define SEL4BENCH_IA32_HASWELL_EVENT_RTM_RETIRED_ABORTED_RARE 0x10C9 |
| #define SEL4BENCH_IA32_HASWELL_EVENT_RTM_RETIRED_ABORTED_HLE 0x20C9 |
| #define SEL4BENCH_IA32_HASWELL_EVENT_RTM_RETIRED_ABORTED_MEM_TYPE 0x40C9 |
| #define SEL4BENCH_IA32_HASWELL_EVENT_RTM_RETIRED_ABORTED_OTHER 0x80C9 |
| |
| |
| //P6 family (PM, P3) |
| //new (or modified) in PM -- note, branch prediction events include speculative execution |
| #define SEL4BENCH_IA32_P6_EVENT_EXECUTE_BRANCH 0x0088 |
| #define SEL4BENCH_IA32_P6_EVENT_BRANCH_MISPREDICT 0x0089 |
| //all P6 processors |
| #define SEL4BENCH_IA32_P6_EVENT_CACHE_L2_LINES_IN 0x0024 //modifiers: PREFETCH, MESI |
| #define SEL4BENCH_IA32_P6_EVENT_CACHE_L2_IFETCH 0x0028 //modifiers: MESI |
| #define SEL4BENCH_IA32_P6_EVENT_CACHE_L2_READ 0x0029 //modifiers: PREFETCH, MESI |
| #define SEL4BENCH_IA32_P6_EVENT_CACHE_L2_WRITE 0x002A //modifiers: MESI |
| #define SEL4BENCH_IA32_P6_EVENT_MAIN_MEMORY_ACCESS 0x0043 |
| #define SEL4BENCH_IA32_P6_EVENT_CACHE_L1D_LINES_IN 0x0045 |
| #define SEL4BENCH_IA32_P6_EVENT_INSTRUCTION_FETCH 0x0080 |
| #define SEL4BENCH_IA32_P6_EVENT_CACHE_L1I_MISS 0x0081 |
| #define SEL4BENCH_IA32_P6_EVENT_TLB_IMISS 0x0085 |
| #define SEL4BENCH_IA32_P6_EVENT_RETIRE_INSTRUCTION 0x00C0 |
| #define SEL4BENCH_IA32_P6_EVENT_RETIRE_BRANCH 0x00C4 |
| #define SEL4BENCH_IA32_P6_EVENT_BRANCH_MISPREDICT_R 0x00C5 |
| #define SEL4BENCH_IA32_P6_EVENT_HARDWARE_INTERRUPT 0x00C8 |
| #define SEL4BENCH_IA32_P6_EVENT_BTB_MISS 0x00E2 |
| |
| //generification layer |
| #define SEL4BENCH_IA32_EVENT_GENERIC_MASK 0xFFFF0000 |
| enum { |
| SEL4BENCH_IA32_EVENT_CACHE_L1I_MISS = 0 | SEL4BENCH_IA32_EVENT_GENERIC_MASK, |
| SEL4BENCH_IA32_EVENT_CACHE_L1D_MISS = 1 | SEL4BENCH_IA32_EVENT_GENERIC_MASK, |
| SEL4BENCH_IA32_EVENT_TLB_L1I_MISS = 2 | SEL4BENCH_IA32_EVENT_GENERIC_MASK, |
| SEL4BENCH_IA32_EVENT_TLB_L1D_MISS = 3 | SEL4BENCH_IA32_EVENT_GENERIC_MASK, |
| SEL4BENCH_IA32_EVENT_MEMORY_ACCESS = 4 | SEL4BENCH_IA32_EVENT_GENERIC_MASK |
| }; |
| #define SEL4BENCH_IA32_EVENT_BRANCH_MISPREDICT 0x00C5 |
| #define SEL4BENCH_IA32_EVENT_EXECUTE_INSTRUCTION 0x00C0 |
| |
