- e7d8643 [test] Fix OpenOCD test breakage introduce by refactoring. by Miguel Young de la Sota · 5 years ago
- f2cc406 [dv] Fix compile warning in tl_seq_item by Weicai Yang · 5 years ago
- 309a479 [prim] Use prim_pkg::impl_e instead of int for Impl by Philipp Wagner · 5 years ago
- cabf26f [prim] Restore ability to select default implementation by Philipp Wagner · 5 years ago
- e7aef11 [boot_rom] Fix README.md naming by Garret Kelly · 5 years ago
- 45859b7 [reggen] Wrap output to meet code standards by Greg Chadwick · 5 years ago
- 8a0c2cb [test] Add an FPGA test executor, similar to the Verilator executor. by Miguel Young de la Sota · 5 years ago
- 6c2a57c [aes/rtl] Fix lint errors by Pirmin Vogel · 5 years ago
- c703936 [templates] Align all doc and script files to use <ext>.tpl by Michael Schaffner · 5 years ago
- 18d6072 [templates] Rename all template files to conform to <ext>.tpl by Michael Schaffner · 5 years ago
- 2f73e4f [doc] Merge Verilator note by Tobias Wölfel · 5 years ago
- ef72c0e [rv_dm] Document the Debug System wrapper by Philipp Wagner · 5 years ago
- 226eab6 [hmac] Re-generate HMAC register and TOP module by Eunchan Kim · 5 years ago
- 14a4312 [hmac] Error Handling: Discard Msg if sha_en:=0 by Eunchan Kim · 5 years ago
- a40dc02 [docgen] Fix two testplans that broke docgen by Michael Schaffner · 5 years ago
- 78778e1 [dv/doc] Memory model documentation by Udi Jonnalagadda · 5 years ago
- 13678cf [hmac] Add Error Reponse for Read of MSG by Eunchan Kim · 5 years ago
- 327ba7e [github] Add additional CODEOWNERS for sw/ by Garret Kelly · 5 years ago
- 7fc62ce [doc] minor fixes to fpga doc by Timothy Chen · 5 years ago
- d07b10e [dv] Update env_cfg template to use parameter ADDR_MAP_SIZE by Weicai Yang · 5 years ago
- cb74aff [site] Add site serving skeleton and scripts by Garret Kelly · 5 years ago
- dae614b [doc/ug] Github commit & merge guide by Eunchan Kim · 5 years ago
- d11f4b9 [doc, fpga] Updates to getting_started guide by Timothy Chen · 5 years ago
- 079aee5 [doc, fpga] Move getting_started_fpga to fpga directory by Timothy Chen · 5 years ago
- 9b4ff65 [doc, fpga] Add FPGA reference manual by Timothy Chen · 5 years ago
- 0b2b599 [doc, fpga] Add FPGA quick start guide by Timothy Chen · 5 years ago
- 4668633 [doc] Add some basic software descriptions by Timothy Chen · 5 years ago
- 7a363d0 [test] Make tests prefer to pass around Paths over strs. by Miguel Young de la Sota · 5 years ago
- 1c14ede [dv, doc] doc & Hjson tesetplan fixes by Srikrishna Iyer · 5 years ago
- aaaad5f [dv] Fix for dv plan template doc by Srikrishna Iyer · 5 years ago
- d76b198 [verilator] update top_earlgrey_usb_verilator to also use ibex verilator by Timothy Chen · 5 years ago
- 999d100 [dpi, verilator] Update spidpi verilator compile issues by Timothy Chen · 5 years ago
- 89606bf [top, verilator] top_earlgrey updates to re-use ibex verilator setup by Timothy Chen · 5 years ago
- 56ebc20 [ibex, verilator] Update ibex vendor script for verilator re-use by Timothy Chen · 5 years ago
- d6f4c7f [sw] Update all C files in SW to use designated initializers. by Miguel Young de la Sota · 5 years ago
- a9f69be [reggen] Correct calculation of interrupt width by Eunchan Kim · 5 years ago
- 11894a6 [prim_ram_2p] Avoid wildcard port list by Philipp Wagner · 5 years ago
- 5cb7022 [prim] Fix various comments by Philipp Wagner · 5 years ago
- c54da18 [style] Require designated initializers for structs/unions. by Miguel Young de la Sota · 5 years ago
- de4201e [test] Decrease compare value for faster testing by Timothy Chen · 5 years ago
- 392aa3e [pinmux] Simplify bitwidth calculation in tpl file by Michael Schaffner · 5 years ago
- 0cd0a40 [alert_handler/dv] Generate DV files and hook up DUT by Michael Schaffner · 5 years ago
- 2e5894d [sw, flash] Minor fix to flash_test for verilator by Timothy Chen · 5 years ago
- 928d523 [dv] documentation and uvmdvgen script updates by Srikrishna Iyer · 5 years ago
- 9e2f893 [lint/prim_fifo_sync] This corrects two lint errors in case of Depth = 1 by Michael Schaffner · 5 years ago
- 41c5b7c [dv, doc] documentation for testplanner tool by Srikrishna Iyer · 5 years ago
- f495ea5 [dv/hmac] add datapath stress test by Cindy Chen · 5 years ago
- 04c8152 [test] Add functional verilator tests. by Miguel Young de la Sota · 5 years ago
- 25b0c66 [doc] Minor updates to fpga doc by Timothy Chen · 5 years ago
- d26ed84 [xbar/dv] Add multiple test to control delay and add out of order by Weicai Yang · 5 years ago
- f57a1b2 [docs] Document rv_core_ibex by Philipp Wagner · 5 years ago
- ddc4ed3 [GPIO/DOC] Minor doc updates following review by Tom Roberts · 5 years ago
- 658d5c6 [dv/hmac] fix hmac dv typo by Cindy Chen · 5 years ago
- 005dbe7 [doc] Fix verilator instructions by Timothy Chen · 5 years ago
- 1a95dd9 [top_earlgrey] Restructure top files by Eunchan Kim · 5 years ago
- d61724d [dv doc] prototype implmentation of hjson testplan by Srikrishna Iyer · 5 years ago
- 6725ffd [dv/common] Add in between reset support in TLUL by Shailendra Kushwah · 5 years ago
- 6637075 [fpga] Fix ROM init file paths and typos by Timothy Chen · 5 years ago
- 444055d [fpga] Minor fixes to splicing by Timothy Chen · 5 years ago
- 698d676 [dv] Update all IP to support tl error cases by Weicai Yang · 5 years ago
- 04b0243 [doc] update hw_stages for DV milestones by Scott Johnson · 5 years ago
- 6b6621d modified: ../../hw/top_earlgrey/data/placement.xdc by Ram Penugonda · 5 years ago
- 1489116 [uart/dv] Fix corner case for tx_empty by Tobias Wölfel · 6 years ago
- 19ab493 [formal] Add assumption for TLUL by Cindy Chen · 5 years ago
- 656a295 [prim_flash] Improve description in core file by Philipp Wagner · 5 years ago
- 6e85f1b [flash_ctrl] Align core file name with design name by Philipp Wagner · 5 years ago
- bada7ed [aes/rtl] Declare functions as automatic by Pirmin Vogel · 5 years ago
- 6824d12 [aes/rtl] Implement Key Expand module by Pirmin Vogel · 5 years ago
- 79aac27 Update lowrisc_ibex to lowRISC/ibex@6b1a7ad by Greg Chadwick · 5 years ago
- 00b6337 [padctrl] Append _pad postfix to pad signals by Michael Schaffner · 5 years ago
- 3bfa986 [hmac/dv] add functional coverage by Cindy Chen · 5 years ago
- 7ba939a [top_earlgrey] Fix documentation how to use topgen by Philipp Wagner · 5 years ago
- 8fccfe2 [Ibex] Fix indentation of top-level parameters by Philipp Wagner · 5 years ago
- a3ec3ba [Ibex] Expose PMP-related parameters in wrapper by Philipp Wagner · 5 years ago
- e7a4041 [aes/rtl] Adjust style of round key mux by Pirmin Vogel · 5 years ago
- 009d38d [aes/rtl] Fix clearing of key and output registers by Pirmin Vogel · 5 years ago
- b5961eb Update pulp_riscv_dbg to pulp-platform/riscv-dbg@811b2d7 by Philipp Wagner · 5 years ago
- 51fcf69 [top_earlgrey] Remove unused file by Alex Bradbury · 5 years ago
- 556c3d7 [dv gpio] Updates related to coverage, gpio weak pull, warnings' cleanup by Gaurang Chitroda · 5 years ago
- 480eaf5 [uart] Remove lines for code coverage by Eunchan Kim · 5 years ago
- b816538 [alert_handler] Small updates in alert handler by Michael Schaffner · 5 years ago
- 40066ff [pinmux] Switch to correct parameter in regfile template by Michael Schaffner · 5 years ago
- 0dc6cd8 [dv/csr_utils] Add more info to CSR error message and fix typos by Michael Schaffner · 5 years ago
- 135321f [formal] add rv_plic assertion by Cindy Chen · 6 years ago
- 13282a4 [aes/rtl] Implement ShiftRows operation by Pirmin Vogel · 5 years ago
- 80bd8aa [topgen] Handle multi clock ports in topgen/module/xbar by Timothy Chen · 5 years ago
- 531b263 [dv/hmac] Update hmac addr size for tl_errors by Weicai Yang · 5 years ago
- 59d2f01 [tlul] Revise full data check. by Eunchan Kim · 5 years ago
- 8d29609 [hmac] Assert Known for outputs by Eunchan Kim · 5 years ago
- b2b8471 [dv/uvmdvgen] Correct typo and hierarchical path of tlul_assert by Michael Schaffner · 5 years ago
- 03cf29f [util/syn_yosys] Add LEC script to check Verilog generated by sv2v by Nils Graf · 6 years ago
- c1453e8 [aes/model] Add missing newline in printf() by Pirmin Vogel · 5 years ago
- 807e709 [aes/rtl] Replace aes_mul* modules by functions by Pirmin Vogel · 5 years ago
- 7f4d3b4 [aes/rtl] Implement MixColumns operation by Pirmin Vogel · 5 years ago
- 54f882e [aes/rtl] Add SubBytes operation by Pirmin Vogel · 5 years ago
- aeca705 [dv] Fix xcelium compile errors by Weicai Yang · 5 years ago
- 7aab759 [dv] Fix compile error due to lack of input of cfg.initialize by Weicai Yang · 5 years ago
- f203e2a [xbar/dv] Update xbar scb by Weicai Yang · 5 years ago
- dead5f4 [dv] TL error - protocol error by Philipp Wagner · 5 years ago
- a8255fd [dv, uvmdvgen] fixes for issue 434 by Srikrishna Iyer · 5 years ago
