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opensecura / 3p / lowrisc / opentitan / 270c637e957461815172b87d080e8ec778e89de0 / hw / ip / otbn / doc
  1. e2bf04d [otbn] Specify memory layout as seen from processor by Philipp Wagner · 4 years, 8 months ago
  2. 31399ae [otbn] Start WSR numbers at zero by Philipp Wagner · 4 years, 9 months ago
  3. 935a910 [otbn] Add ACC access via WSRs by Greg Chadwick · 4 years, 9 months ago
  4. 63da48e Extract OTBN ISA documentation into a YAML file by Rupert Swarbrick · 4 years, 9 months ago
  5. 9870373 [doc] Fix 128x128 BN.MULQACC example in OTBN docs by Greg Chadwick · 4 years, 9 months ago
  6. de5f9f3 [OTBN] fix inconsitency in spec by Felix Miller · 4 years, 10 months ago
  7. 99e9f7f [otbn] Fix rendering of WSR table in spec by Philipp Wagner · 4 years, 10 months ago
  8. 05a5f14 [otbn] OpenTitan Big Number Accelerator Specification, v0.1 by Philipp Wagner · 4 years, 10 months ago