| commit | 05a5f14ede7c69b49402245fff3928e7f2750289 | [log] [tgz] |
|---|---|---|
| author | Philipp Wagner <phw@lowrisc.org> | Wed Jun 03 23:42:20 2020 +0100 |
| committer | Philipp Wagner <mail@philipp-wagner.com> | Wed Jun 17 21:20:32 2020 +0100 |
| tree | 7346f5e7b12355d8191fd42ab27200db8d5fa759 | |
| parent | f1fa7c1e92ca71b3c4b473317bfc14f8deb93bf2 [diff] |
[otbn] OpenTitan Big Number Accelerator Specification, v0.1 Say hello to OTBN, the imaginative name for the OpenTitan Big Number Accelerator. OTBN is a co-processor designed to quickly compute algorithms which rely on wide integer arithmetic, primarily public key cytography. Think RSA and ECDSA. OTBN is a self-contained IP block and consists (on a very high level) of a CPU, accompanied by a dedicated instruction and data memory. The core of this specification is the instruction set architecture (ISA) of OTBN. The ISA consists of two parts: a base instruction subset for the control flow, and a big number instruction subset for wide integer arithmetic. The base instruction subset is based on an extended subset of RISC-V's RV32I_Zisr. Even though many instructions are identical to their RV32I couterpart, OTBN is *not* a standards-compliant RISC-V processor. The big number instruction subset processes 256 bit wide data words. It operates on a equally wide register file of 32 256b wide registers. A lot of thought has been put into efficient multiplications of wide integers, which resulted in the design of a 64 x 64 bit multiply-accumulate instruction, which can be effectively combined to multiply 256b words in 16 instructions. A word of caution: The specification as it is presented in this commit is not the "final" OTBN specification -- it is version 0.1 and marks a starting point in the design of this IP block. The specification has known holes, and has not yet incorporated all simplifications and features we have thought of and require for the "final" OTBN. We encourage ideas, suggestions, and critique in the form of issues, which we can then sort through and incorporate into subsequent versions of this specification. Furthermore, the implementation work on OTBN has not yet started. We expect to incorporate the learnings from our implementation, hardening, and verification work to feed back into the specification. The specification in this commit has been developed over the course of more than half a year with a huge amount of work done by Felix Miller with input from Greg Chadwick, Timothy Chen, Chris Gori, Miguel Osorio, Stefan Wallentowitz, and many others. Thank you! Signed-off-by: Philipp Wagner <phw@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.
Have a look at CONTRIBUTING for guidelines on how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).
