blob: fe66e88482e46e01f190c2abfa21640a93448ff0 [file] [log] [blame]
Madhuri Patel3cb47a02021-11-11 15:35:55 +00001// Copyright lowRISC contributors.
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4{
5 name: "sysrst_ctrl"
Madhuri Patel3cb47a02021-11-11 15:35:55 +00006 import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
Madhuri Patel706a2b92021-11-25 15:32:00 +00007 "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
Madhuri Patel3cb47a02021-11-11 15:35:55 +00008 "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
Madhuri Patel706a2b92021-11-25 15:32:00 +00009 "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
Srikrishna Iyera463e172022-02-02 12:09:39 -080010 "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
11 "sysrst_ctrl_sec_cm_testplan.hjson"]
Madhuri Patel3cb47a02021-11-11 15:35:55 +000012 testpoints: [
13 {
14 name: smoke
15 desc: '''
Madhuri Patel706a2b92021-11-25 15:32:00 +000016 Verify end to end data transfer in normal operation mode.
Madhuri Patel3cb47a02021-11-11 15:35:55 +000017
Madhuri Patel706a2b92021-11-25 15:32:00 +000018 * Write a random data to the input keys.
19 * Read the data at the output pins and compare it with the input data.
Madhuri Patel3cb47a02021-11-11 15:35:55 +000020 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070021 stage: V1
Madhuri Patel3cb47a02021-11-11 15:35:55 +000022 tests: ["sysrst_ctrl_smoke"]
23 }
Madhuri Patel706a2b92021-11-25 15:32:00 +000024
Madhuri Patel3cb47a02021-11-11 15:35:55 +000025 {
Madhuri Patel706a2b92021-11-25 15:32:00 +000026 name: input_output_inverted
27 desc: '''
28 Verify end to end data transfer with inverted input and inverted output.
29
30 * Write a random data to the input keys.
Marno van der Maas065d0e42023-02-02 11:53:18 +000031 * Randomly configure KEY_INVERT_CTL to invert or not invert inputs and outputs.
32 * In case of no inversions or inverting both check that input matches output.
33 * In case where the input is inverted but not the output or the other way around check that input does not match output.
Madhuri Patel706a2b92021-11-25 15:32:00 +000034 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070035 stage: V1
Madhuri Patel706a2b92021-11-25 15:32:00 +000036 tests: ["sysrst_ctrl_in_out_inverted"]
37 }
38
39 {
40 name: combo_detect_ec_rst
41 desc: '''
42 Verify the combo detection with ec_rst action.
Srikrishna Iyera463e172022-02-02 12:09:39 -080043
Marno van der Maas065d0e42023-02-02 11:53:18 +000044 * Set the input keys by configuring COM_SEL_CTL_0 register.
Srikrishna Iyera463e172022-02-02 12:09:39 -080045 * Set the combo duration via the COM_DET_CTL_0 register.
46 * Select the action to be taken by configuring COM_OUT_CTL_0 register.
47 * Set the pulse width via EC_RST_CTL register only to raise ec_rst action.
Marno van der Maas065d0e42023-02-02 11:53:18 +000048 * Drive the input with a randomized delay.
49 * Read the COMBO_INTR_STATUS register.
50 In case the input was driven for longer than the debounce delay, check if the interrupt is raised and clear the interrupt.
Madhuri Patel706a2b92021-11-25 15:32:00 +000051 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070052 stage: V1
Madhuri Patel706a2b92021-11-25 15:32:00 +000053 tests: ["sysrst_ctrl_combo_detect_ec_rst"]
54 }
55
56 {
Cindy Chen09ed7c42023-02-02 10:34:10 -080057 name: combo_detect_ec_rst_with_pre_cond
58 desc: '''
59 Verify the pre-condition for combo detection.
60
61 * Define `pwrb_in == 0` as a pre-condition by writing the COM_PRE_SEL_CTL_0 register
62 with value 'h8.
63 * Set the pre-condition duration time via the `COM_PRE_DET_CTL` register.
64 * Wait for the pre-condition to be satisfied.
65 * Trigger the combo_detect_ec_rst sequence.
66 * NOTE: This is a directed test with no random values for V1 stage,
67 further this test will be randomized.
68 '''
69 stage: V1
70 tests: ["sysrst_ctrl_combo_detect_ec_rst_with_pre_cond"]
71 }
72
73 {
Madhuri Patel706a2b92021-11-25 15:32:00 +000074 name: combo_detect
75 desc: '''
76 Verify the combo detection with random action.
Srikrishna Iyera463e172022-02-02 12:09:39 -080077
Marno van der Maas065d0e42023-02-02 11:53:18 +000078 * Randomly set the input keys by configuring COM_SEL_CTL_0-3 register.
79 * Set the random combo duration via the COM_DET_CTL_0-3 register.
80 * Randomly select the action to be taken by configuring COM_OUT_CTL_0-3 register.
Srikrishna Iyera463e172022-02-02 12:09:39 -080081 * Set the pulse width via EC_RST_CTL register.
Marno van der Maas065d0e42023-02-02 11:53:18 +000082 * Read the COMBO_INTR_STATUS register to check whether an interrupt is correctly raised for all the combinations.
83 Clear the interrupt in case it was raised.
Madhuri Patel706a2b92021-11-25 15:32:00 +000084 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070085 stage: V2
Madhuri Patel706a2b92021-11-25 15:32:00 +000086 tests: ["sysrst_ctrl_combo_detect"]
87 }
88
89 {
Raviteja Chatta4bebd712023-02-23 10:52:00 +000090 name: combo_detect_with_pre_cond
91 desc: '''
92 Verify the combo detection with random action and precondition.
93
94 * Randomly set the input keys combination as precondition by configuring COM_PRE_SEL_CTL_0-3 register.
95 * Randomly set the input keys combination for combo detection by configuring COM_SEL_CTL_0-3 register.
96 * Set the random combo precondition duration via the COM_PRE_DET_CTL_0-3 register.
97 * Set the random combo duration via the COM_DET_CTL_0-3 register.
98 * Randomly select the action to be taken by configuring COM_OUT_CTL_0-3 register.
99 * Set the pulse width via EC_RST_CTL register.
100 * Randomly set the input keys, such that precondition and subsequent combo detection logic are activated randomly.
101 * Read the COMBO_INTR_STATUS register to check whether an interrupt is correctly raised for all the combinations.
102 Clear the interrupt in case it was raised.
103 * Check for bat_disable, rst_req or wake_up_o assertion depending on COM_OUT_CTL_0-3 register
104 '''
105 stage: V2
106 tests: ["sysrst_ctrl_combo_detect_with_pre_cond"]
107 }
108
109 {
Madhuri Patel706a2b92021-11-25 15:32:00 +0000110 name: auto_block_key_outputs
111 desc: '''
112 Verify the auto block key output feature.
113
114 * Trigger the input keys combo.
Srikrishna Iyera463e172022-02-02 12:09:39 -0800115 * Set the debounce timer value in AUTO_BLOCK_DEBOUNCE_CTL register.
Madhuri Patel706a2b92021-11-25 15:32:00 +0000116 * Select the output override value by configuring AUTO_BLOCK_OUT_CTL register.
Srikrishna Iyera463e172022-02-02 12:09:39 -0800117 * Check whether the input keys stays low for the selected debounce time.
Madhuri Patel706a2b92021-11-25 15:32:00 +0000118 * Read the AUTO_BLOCK_OUT_CTL register to check if the output key is overridden.
119 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700120 stage: V2
Madhuri Patel706a2b92021-11-25 15:32:00 +0000121 tests: ["sysrst_ctrl_auto_blk_key_output"]
122 }
123
124 {
125 name: keyboard_input_triggered_interrupt
126 desc: '''
Srikrishna Iyera463e172022-02-02 12:09:39 -0800127 Verify the keyboard and input triggered interrupt feature by detecting the edge
Madhuri Patel706a2b92021-11-25 15:32:00 +0000128 transitions on input pins.
129
Srikrishna Iyera463e172022-02-02 12:09:39 -0800130 * Set the input signals and edge transition by configuring KEY_INTR_CTL register.
131 * Set the debounce timer value via KEY_INTR_DEBOUNCE_CTL register.
Marno van der Maas065d0e42023-02-02 11:53:18 +0000132 * Read the KEY_INTR_STATUS register to check if the interrupt caused and clear the interrupt.
Madhuri Patel706a2b92021-11-25 15:32:00 +0000133 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700134 stage: V2
Madhuri Patel706a2b92021-11-25 15:32:00 +0000135 tests: ["sysrst_ctrl_edge_detect"]
136 }
137
138 {
139 name: pin_output_keyboard_inversion_control
140 desc: '''
141 Verify the keyboard inversion feature by override logic.
142
Srikrishna Iyera463e172022-02-02 12:09:39 -0800143 * Select the output signals to override via PIN_OUT_CTL register.
Madhuri Patel706a2b92021-11-25 15:32:00 +0000144 * Allow the output signals to override the value via PIN_ALLOWED_CTL register.
145 * Set the override value to the output signal via PIN_OUT_VALUE register.
Marno van der Maas065d0e42023-02-02 11:53:18 +0000146 * Check whether the override happens correctly.
Madhuri Patel706a2b92021-11-25 15:32:00 +0000147 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700148 stage: V2
Marno van der Maas05efd892023-02-02 11:29:14 +0000149 tests: ["sysrst_ctrl_pin_override_test"]
Madhuri Patel706a2b92021-11-25 15:32:00 +0000150 }
151
152 {
153 name: pin_input_value_accessibility
154 desc: '''
155 Verify the pin input value accessibilty.
156
Marno van der Maas065d0e42023-02-02 11:53:18 +0000157 * Trigger the key[0,1,2], ac_present_in, pwrb_in, ec_rst_in_l input pins with random values.
Madhuri Patel706a2b92021-11-25 15:32:00 +0000158 * Read the PIN_IN_VALUE register and check if the read value is same as input value.
159 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700160 stage: V2
Madhuri Patel706a2b92021-11-25 15:32:00 +0000161 tests: ["sysrst_ctrl_pin_access_test"]
162 }
163
164 {
165 name: ec_power_on_reset
166 desc: '''
167 Verify the EC and power on reset.
168
Marno van der Maas065d0e42023-02-02 11:53:18 +0000169 * Disable EC reset override.
170 * Set EC reset timer to stretch reset.
171 * Make sure ec_rst_out_l is asserted even after OpenTitan reset is released.
Madhuri Patel706a2b92021-11-25 15:32:00 +0000172 * Set PIN_OUT_CTL.EC_RST_L to 0 to release the ec_rst_out_l reset.
173 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700174 stage: V2
Madhuri Patel706a2b92021-11-25 15:32:00 +0000175 tests: ["sysrst_ctrl_ec_pwr_on_rst"]
176 }
177
178 {
179 name: flash_write_protect_output
180 desc: '''
181 Verify the flash write protect.
182
183 * Make sure flash_wp_out_l signal is asserted low by reading PIN_OUT_CTL.flash_wp_l.
Srikrishna Iyera463e172022-02-02 12:09:39 -0800184 * Enable the override function by setting PIN_OUT_CTL.FLASH_WP_L to value 1.
Madhuri Patel30036d22022-03-31 14:49:35 +0100185 * Randomize the corresponding flash_wp_l_i input pin.
186 * Check flash_wp_l_i does not have a bypass path to flash_wp_l_o.
187 * Check if flash_wp_l_o is released only by the override function.
Madhuri Patel706a2b92021-11-25 15:32:00 +0000188 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700189 stage: V2
Madhuri Patel706a2b92021-11-25 15:32:00 +0000190 tests: ["sysrst_ctrl_flash_wr_prot_out"]
191 }
192
193 {
194 name: ultra_low_power_test
195 desc: '''
Srikrishna Iyera463e172022-02-02 12:09:39 -0800196 Verify the ultra low power feature.
Madhuri Patel706a2b92021-11-25 15:32:00 +0000197
Marno van der Maas065d0e42023-02-02 11:53:18 +0000198 * Configure ULP_AC_DEBOUNCE_CTL, ULP_LID_DEBOUNCE_CTL and ULP_PWRB_DEBOUNCE_CTL register to set the debounce timer value.
Madhuri Patel706a2b92021-11-25 15:32:00 +0000199 * Disable the bus clock to check detection logic works in sleep mode.
Marno van der Maas065d0e42023-02-02 11:53:18 +0000200 * Trigger the ac_present_i, lid_open_in and ec_rst_l_i input keys.
Srikrishna Iyera463e172022-02-02 12:09:39 -0800201 * Turn on the bus clock to read the status register.
202 * Read the WKUP_STATUS register to check if the event has occured.
Marno van der Maas065d0e42023-02-02 11:53:18 +0000203 * Read the ULP_STATUS register and check if the ultra low power wakeup event is detected.
Madhuri Patel706a2b92021-11-25 15:32:00 +0000204 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700205 stage: V2
Madhuri Patel706a2b92021-11-25 15:32:00 +0000206 tests: ["sysrst_ctrl_ultra_low_pwr"]
Madhuri Patel3cb47a02021-11-11 15:35:55 +0000207 }
Madhuri Patel30036d22022-03-31 14:49:35 +0100208
209 {
210 name: stress_all
211 desc: '''
212 Test all the sequences randomly in one sequence.
213
214 * Combine above sequences in one test then randomly select for running.
215 * All sequences should be finished and checked by the scoreboard.
216 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700217 stage: V2
Madhuri Patel30036d22022-03-31 14:49:35 +0100218 tests: ["sysrst_ctrl_stress_all"]
219 }
Madhuri Patel3cb47a02021-11-11 15:35:55 +0000220 ]
221
222 covergroups: [
223 {
Madhuri Patel706a2b92021-11-25 15:32:00 +0000224 name: sysrst_ctrl_combo_detect_action_cg
225 desc: '''
Raviteja Chatta3f69ac52023-02-16 10:12:11 +0000226 Cover all the combo detect, combo_sel and combo_pre_sel actions.
Madhuri Patel30036d22022-03-31 14:49:35 +0100227 Create 4 instance to cover the combo detect register [0-3].
228 Sample the covergroup when the event occurs.
Raviteja Chatta3f69ac52023-02-16 10:12:11 +0000229 Cross the covergroup with combo_detect_sel_cg and combo_pre_sel_cg to cover all the input combination with
Madhuri Patel30036d22022-03-31 14:49:35 +0100230 all the possible combo_detect actions.
231 '''
232 }
233 {
234 name: sysrst_ctrl_combo_detect_det_cg
235 desc: '''
236 Cover the combo detect debounce timer.
237 Create 4 instance to cover the combo detect register [0-3].
238 '''
239 }
240 {
Raviteja Chatta3f69ac52023-02-16 10:12:11 +0000241 name: sysrst_ctrl_combo_precondition_det_cg
242 desc: '''
243 Cover the combo detect precondition debounce timer.
244 Create 4 instance to cover the combo detect precondition register [0-3].
245 '''
246 }
247 {
Madhuri Patel30036d22022-03-31 14:49:35 +0100248 name: sysrst_ctrl_auto_block_debounce_ctl_cg
249 desc: '''
250 Cover the auto block enable/disable feature.
251 Cover the auto block debounce timer.
252 '''
253 }
254 {
255 name: sysrst_ctrl_combo_intr_status_cg
256 desc: '''
257 Cover the combo detect status of all 4 set of combo registers.
258 Cover all the input combinations has generated selected outcome actions and cross
259 with the status generated.
260 '''
261 }
262 {
263 name: sysrst_ctrl_key_intr_status_cg
264 desc: '''
265 Cover the H2L/L2H edge detect event of all the inputs.
266 '''
267 }
268 {
269 name: sysrst_ctrl_ulp_status_cg
270 desc: '''
271 Cover the ultra low power event triggered.
272 Cover the following condition triggers the ultra low power event:
273 * High to low transition on pwrb_in input pin
274 * Low to High transition on lid_open pin.
275 * A level high on ac_present pin.
276 Cross the above three condition with the ulp_status.
277 '''
278 }
279 {
280 name: sysrst_ctrl_wkup_event_cg
281 desc: '''
282 Cover the ultra low power wakeup event and status.
283 Cover the wkup event could occur due to following condition:
284 * High to low transition on pwrb_in input pin when ulp feature is enable.
285 * Low to High transition on lid_open pin when ulp feature is enable.
286 * A level high on ac_present pin when ulp feature is enable.
287 * When an interrupt is generated.
288 Cross the above condition with the wkup_status register.
289 '''
290 }
291 {
292 name: sysrst_ctrl_key_invert_ctl_cg
293 desc: '''
294 Cover the invert values of all input and output values.
295 '''
296 }
297 {
298 name: sysrst_ctrl_pin_in_value_cg
299 desc: '''
300 Cover the raw input values before inversion for all inputs.
301 '''
302 }
303 {
304 name: sysrst_ctrl_auto_blk_out_ctl_cg
305 desc: '''
306 Cover the auto blk input select and their values.
307 Cross the key outputs selected to override with their override values.
308 Sample the covergroup when the event occurs.
309 '''
310 }
311 {
312 name: pin_cfg_cg
313 desc: '''
314 Cover the override enable/disable of all the inputs.
315 Cover the override values of all the input values.
316 Cover the allowed value 0 and 1 of all the inputs.
317 Cross all the above coverpoints.
318 '''
319 }
320 {
321 name: debounce_timer_cg
322 desc: '''
323 Cover the debounce timer of the following registers
324 * ec_rst_ctl register.
325 * key_intr_debounce_ctl register.
326 * ulp_ac_debounce_ctl register.
327 * ulp_pwrb_debounce_ctl register.
328 * ulp_lid_debounce_ctl register.
Madhuri Patel706a2b92021-11-25 15:32:00 +0000329 '''
Madhuri Patel3cb47a02021-11-11 15:35:55 +0000330 }
331 ]
332}