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opensecura / 3p / lowrisc / opentitan / e7e8559fc9e7aaebc0041fca789082cb3118e655 / . / hw / ip / gpio / doc / checklist.md
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Eunchan Kimc1be7eb2019-10-29 11:50:29 -0700[diff] [blame]1---
2title: "GPIO Checklist"
3---
4
5This checklist is for [Hardware Stage]({{<relref "/doc/project/hw_stages.md">}}) transitions for the [GPIO peripheral][GPIO Spec].
6All checklist items refer to the content in the [Checklist.]({{<relref "/doc/project/checklist.md">}})
7
8## Design Checklist
9
10### D1
11
12Type | Item | Resolution | Note/Collaterals
13--------------|-----------------------|-------------|------------------
14Documentation | [SPEC_COMPLETE][] | Done | [GPIO Spec][]
15Documentation | [CSR_DEFINED][] | Done | [GPIO CSR][]
16RTL | [CLKRST_CONNECTED][] | Done |
17RTL | [IP_TOP][] | Done |
18RTL | [IP_INSTANCED][] | Done |
19RTL | [MEM_INSTANCED_80][] | N/A |
20RTL | [FUNC_IMPLEMENTED][] | Done |
21RTL | [ASSERT_KNOWN_ADDED][]| Done |
22Code Quality | [LINT_SETUP][] | Done |
23Review | Reviewer(s) | Done | @sjgitty @gaurangchitroda
24Review | Signoff date | Done | 2019-10-30
25
26[GPIO Spec]: ../
27[GPIO CSR]: ../data/gpio.hjson
28
29
30[SPEC_COMPLETE]: {{<relref "/doc/project/checklist.md#spec-complete" >}}
31[CSR_DEFINED]: {{<relref "/doc/project/checklist.md#csr-defined" >}}
32[CLKRST_CONNECTED]: {{<relref "/doc/project/checklist.md#clkrst-connected" >}}
33[IP_TOP]: {{<relref "/doc/project/checklist.md#ip-top" >}}
34[IP_INSTANCED]: {{<relref "/doc/project/checklist.md#ip-instanced" >}}
35[MEM_INSTANCED_80]: {{<relref "/doc/project/checklist.md#mem-instanced-80" >}}
36[FUNC_IMPLEMENTED]: {{<relref "/doc/project/checklist.md#func-implemented" >}}
37[ASSERT_KNOWN_ADDED]: {{<relref "/doc/project/checklist.md#assert-known-added" >}}
38[LINT_SETUP]: {{<relref "/doc/project/checklist.md#lint-setup" >}}
39[D1_REVIEWED]: {{<relref "/doc/project/checklist.md#d1-reviewed" >}}
40
41### D2
42
43Type | Item | Resolution | Note/Collaterals
44--------------|-------------------------|-------------|------------------
45Documentation | [NEW_FEATURES][] | N/A |
46Documentation | [BLOCK_DIAGRAM][] | N/A |
47Documentation | [DOC_INTERFACE][] | Done |
48Documentation | [MISSING_FUNC][] | N/A |
49Documentation | [FEATURE_FROZEN][] | Done |
50RTL | [FEATURE_COMPLETE][] | Done |
51RTL | [AREA_SANITY_CHECK][] | Done |
52RTL | [PORT_FROZEN][] | Done |
53RTL | [ARCHITECTURE_FROZEN][] | Done |
54RTL | [REVIEW_TODO][] | Done |
55RTL | [STYLE_X][] | N/A | No assignment of X
56Code Quality | [LINT_PASS][] | Done | Lint waivers reviewed
57Code Quality | [CDC_SETUP][] | N/A | No CDC path
58Code Quality | [FPGA_TIMING][] | Done | Fmax 50MHz on NexysVideo
59Code Quality | [CDC_SYNCMACRO][] | N/A |
60Review | Reviewer(s) | Done | @sjgitty @gaurangchitroda @aytong
61Review | Signoff date | Done | 2019-10-30
62
63[NEW_FEATURES]: {{<relref "/doc/project/checklist.md#new-features" >}}
64[BLOCK_DIAGRAM]: {{<relref "/doc/project/checklist.md#block-diagram" >}}
65[DOC_INTERFACE]: {{<relref "/doc/project/checklist.md#doc-interface" >}}
66[MISSING_FUNC]: {{<relref "/doc/project/checklist.md#missing-func" >}}
67[FEATURE_FROZEN]: {{<relref "/doc/project/checklist.md#feature-frozen" >}}
68[FEATURE_COMPLETE]: {{<relref "/doc/project/checklist.md#feature-complete" >}}
69[AREA_SANITY_CHECK]: {{<relref "/doc/project/checklist.md#area-sanity-check" >}}
70[DEBUG_BUS]: {{<relref "/doc/project/checklist.md#debug-bus" >}}
71[PORT_FROZEN]: {{<relref "/doc/project/checklist.md#port-frozen" >}}
72[ARCHITECTURE_FROZEN]: {{<relref "/doc/project/checklist.md#architecture-frozen" >}}
73[REVIEW_TODO]: {{<relref "/doc/project/checklist.md#review-todo" >}}
74[STYLE_X]: {{<relref "/doc/project/checklist.md#style-x" >}}
75[STYLE_LINT_SETUP]: {{<relref "/doc/project/checklist.md#style-lint-setup" >}}
76[LINT_PASS]: {{<relref "/doc/project/checklist.md#lint-pass" >}}
77[CDC_SETUP]: {{<relref "/doc/project/checklist.md#cdc-setup" >}}
78[CDC_SYNCMACRO]: {{<relref "/doc/project/checklist.md#cdc-syncmacro" >}}
79[FPGA_TIMING]: {{<relref "/doc/project/checklist.md#fpga-timing" >}}
80[D2_REVIEWED]: {{<relref "/doc/project/checklist.md#d2-reviewed" >}}
81
82### D3
83
84 Type | Item | Resolution | Note/Collaterals
85--------------|-------------------------|-------------|------------------
86Documentation | [NEW_FEATURES_D3][] | N/A |
87RTL | [TODO_COMPLETE][] | Done | No TODO
88Code Quality | [LINT_COMPLETE][] | Done |
89Code Quality | [CDC_COMPLETE][] | N/A |
90Review | [REVIEW_RTL][] | Done | Reviewed by @msfschaffner
91Review | [REVIEW_DELETED_FF][] | N/A | Not reported by FPGA tool
92Review | [REVIEW_SW_CSR][] | Done |
93Review | [REVIEW_SW_FATAL_ERR][] | Done |
94Review | [REVIEW_SW_CHANGE][] | Done |
95Review | [REVIEW_SW_ERRATA][] | Done |
96Review | Reviewer(s) | Done | @gkelly @sjgitty @gaurangchitroda
97Review | Signoff date | Done | 2019-11-04
98
99[NEW_FEATURES_D3]: {{<relref "/doc/project/checklist.md#new-features-d3" >}}
100[TODO_COMPLETE]: {{<relref "/doc/project/checklist.md#todo-complete" >}}
101[LINT_COMPLETE]: {{<relref "/doc/project/checklist.md#lint-complete" >}}
102[CDC_COMPLETE]: {{<relref "/doc/project/checklist.md#cdc-complete" >}}
103[REVIEW_RTL]: {{<relref "/doc/project/checklist.md#review-rtl" >}}
104[REVIEW_DBG]: {{<relref "/doc/project/checklist.md#review-dbg" >}}
105[REVIEW_DELETED_FF]: {{<relref "/doc/project/checklist.md#review-deleted-ff" >}}
106[REVIEW_SW_CSR]: {{<relref "/doc/project/checklist.md#review-sw-csr" >}}
107[REVIEW_SW_FATAL_ERR]: {{<relref "/doc/project/checklist.md#review-sw-fatal-err" >}}
108[REVIEW_SW_CHANGE]: {{<relref "/doc/project/checklist.md#review-sw-change" >}}
109[REVIEW_SW_ERRATA]: {{<relref "/doc/project/checklist.md#review-sw-errata" >}}
110[D3_REVIEWED]: {{<relref "/doc/project/checklist.md#d3-reviewed" >}}
111
112## Verification Checklist
113
114### V1
115
116 Type | Item | Resolution | Note/Collaterals
117--------------|---------------------------------------|-----------------|------------------
Gaurang Chitrodae7e85592019-11-04 18:02:17 -0800[diff] [blame^]118Documentation | [DV_PLAN_DRAFT_COMPLETED][] | Done | [gpio_dv_plan][{{<relref "dv_plan/" >}}]
Eunchan Kimc1be7eb2019-10-29 11:50:29 -0700[diff] [blame]119Documentation | [TESTPLAN_COMPLETED][] | Done |
120Testbench | [TB_TOP_CREATED][] | Done |
121Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
122Testbench | [TB_ENV_CREATED][] | Done |
123Testbench | [RAL_MODEL_GEN_AUTOMATED][] | Done |
124Testbench | [TB_GEN_AUTOMATED][] | N/A |
125Tests | [SANITY_TEST_PASSING][] | Done |
126Tests | [CSR_MEM_TEST_SUITE_PASSING][] | Done |
127Tool Setup | [ALT_TOOL_SETUP][] | Done |
128Regression | [SANITY_REGRESSION_SETUP][] | Done w/ waivers | Exception (implemented in local)
129Regression | [NIGHTLY_REGRESSION_SETUP][] | Done w/ waivers | Exception (implemented in local)
130Coverage | [COVERAGE_MODEL_ADDED][] | Done |
131Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | N/A |
132Review | [DESIGN_SPEC_REVIEWED][] | Done |
133Review | [DV_PLAN_TESTPLAN_REVIEWED][] | Done |
134Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | Exception (Security, Power, Debug)
135Review | [V2_CHECKLIST_SCOPED][] | Done |
136Review | Reviewer(s) | Done | @eunchan @sjgitty @sriyerg
137Review | Signoff date | Done | 2019-10-30
138
139[gpio_dv_plan]: {{<relref "/hw/ip/gpio/doc/dv_plan/index.md">}}
140
141[DV_PLAN_DRAFT_COMPLETED]: {{<relref "/doc/project/checklist.md#dv-plan-draft-completed" >}}
142[TESTPLAN_COMPLETED]: {{<relref "/doc/project/checklist.md#testplan-completed" >}}
143[TB_TOP_CREATED]: {{<relref "/doc/project/checklist.md#tb-top-created" >}}
144[PRELIMINARY_ASSERTION_CHECKS_ADDED]: {{<relref "/doc/project/checklist.md#preliminary-assertion-checks-added" >}}
145[TB_ENV_CREATED]: {{<relref "/doc/project/checklist.md#tb-env-created" >}}
146[RAL_MODEL_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#ral-model-gen-automated" >}}
147[TB_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#tb-gen-automated" >}}
148[SANITY_TEST_PASSING]: {{<relref "/doc/project/checklist.md#sanity-test-passing" >}}
149[CSR_MEM_TEST_SUITE_PASSING]: {{<relref "/doc/project/checklist.md#csr-mem-test-suite-passing" >}}
150[ALT_TOOL_SETUP]: {{<relref "/doc/project/checklist.md#alt-tool-setup" >}}
151[SANITY_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#sanity-regression-setup" >}}
152[NIGHTLY_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#nightly-regression-setup" >}}
153[COVERAGE_MODEL_ADDED]: {{<relref "/doc/project/checklist.md#coverage-model-added" >}}
154[PRE_VERIFIED_SUB_MODULES_V1]: {{<relref "/doc/project/checklist.md#pre-verified-sub-modules-v1" >}}
155[DESIGN_SPEC_REVIEWED]: {{<relref "/doc/project/checklist.md#design-spec-reviewed" >}}
156[DV_PLAN_TESTPLAN_REVIEWED]: {{<relref "/doc/project/checklist.md#dv-plan-testplan-reviewed" >}}
157[STD_TEST_CATEGORIES_PLANNED]: {{<relref "/doc/project/checklist.md#std-test-categories-planned" >}}
158[V2_CHECKLIST_SCOPED]: {{<relref "/doc/project/checklist.md#v2-checklist-scoped" >}}
159
160### V2
161
162 Type | Item | Resolution | Note/Collaterals
163--------------|-----------------------------------------|-------------|------------------
164Documentation | [DESIGN_DELTAS_CAPTURED][] | N/A |
165Documentation | [DV_PLAN_COMPLETED][] | Done |
166Testbench | [ALL_INTERFACES_EXERCISED][] | Done |
167Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done |
168Testbench | [TB_ENV_COMPLETED][] | Done |
169Tests | [ALL_TESTS_PASSING][] | Done | Resolved: [#680][]
170Tests | [FW_SIMULATED][] | N/A |
171Regression | [NIGHTLY_REGRESSION_V2][] | Done |
172Coverage | [CODE_COVERAGE_V2][] | Done |
Gaurang Chitrodae7e85592019-11-04 18:02:17 -0800[diff] [blame^]173Coverage | [FUNCTIONAL_COVERAGE_V2][] | Done | Resolved: [#807][]
Eunchan Kimc1be7eb2019-10-29 11:50:29 -0700[diff] [blame]174Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done |
175Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done | [#41][] Not quite related, [#45][] root caused
176Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | N/A |
177Review | [V3_CHECKLIST_SCOPED][] | Done |
178Review | Reviewer(s) | Done | @sjgitty @eunchan @sriyerg
179Review | Signoff date | Done | 2019-11-04
180
181[#41]: https://github.com/lowRISC/opentitan/issues/41
182[#45]: https://github.com/lowRISC/opentitan/issues/45
183[#680]: https://github.com/lowRISC/opentitan/pull/680
Gaurang Chitrodae7e85592019-11-04 18:02:17 -0800[diff] [blame^]184[#807]: https://github.com/lowRISC/opentitan/pull/807
Eunchan Kimc1be7eb2019-10-29 11:50:29 -0700[diff] [blame]185
186[DESIGN_DELTAS_CAPTURED]: {{<relref "/doc/project/checklist.md#design-deltas-captured" >}}
187[DV_PLAN_COMPLETED]: {{<relref "/doc/project/checklist.md#dv-plan-completed" >}}
188[ALL_INTERFACES_EXERCISED]: {{<relref "/doc/project/checklist.md#all-interfaces-exercised" >}}
189[ALL_ASSERTION_CHECKS_ADDED]: {{<relref "/doc/project/checklist.md#all-assertion-checks-added" >}}
190[TB_ENV_COMPLETED]: {{<relref "/doc/project/checklist.md#tb-env-completed" >}}
191[ALL_TESTS_PASSING]: {{<relref "/doc/project/checklist.md#all-tests-passing" >}}
192[FW_SIMULATED]: {{<relref "/doc/project/checklist.md#fw-simulated" >}}
193[NIGHTLY_REGRESSION_V2]: {{<relref "/doc/project/checklist.md#nightly-regression-v2" >}}
194[CODE_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#code-coverage-v2" >}}
195[FUNCTIONAL_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#functional-coverage-v2" >}}
196[NO_HIGH_PRIORITY_ISSUES_PENDING]: {{<relref "/doc/project/checklist.md#no-high-priority-issues-pending" >}}
197[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:{{<relref "/doc/project/checklist.md#all-low-priority-issues-root-caused" >}}
198[PRE_VERIFIED_SUB_MODULES_V2]: {{<relref "/doc/project/checklist.md#pre-verified-sub-modules-v2" >}}
199[V3_CHECKLIST_SCOPED]: {{<relref "/doc/project/checklist.md#v3-checklist-scoped" >}}
200
201### V3
202
203 Type | Item | Resolution | Note/Collaterals
204--------------|-----------------------------------|-------------|------------------
205Documentation | [DESIGN_DELTAS_CAPTURED_IF_ANY][] | N/A |
206Testbench | [ALL_TODOS_RESOLVED][] | Done |
207Tests | [X_PROP_ANALYSIS_COMPLETED][] | Waived | Revisit later. Tool setup in progress.
208Regression | [NIGHTLY_REGRESSION_AT_100][] | Done | Resolved: [#680][]
Gaurang Chitrodae7e85592019-11-04 18:02:17 -0800[diff] [blame^]209Coverage | [CODE_COVERAGE_AT_100][] | Done | [common_cov_excl.el][], [gpio_cov_excl.el][]
Eunchan Kimc1be7eb2019-10-29 11:50:29 -0700[diff] [blame]210Coverage | [FUNCTIONAL_COVERAGE_AT_100][] | Done | [#807][]
211Issues | [NO_ISSUES_PENDING][] | Done |
212Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Done |
213Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | N/A |
214Review | Reviewer(s) | Done | @eunchan @sriyerg @sjgitty
215Review | Signoff date | Done | 2019-11-04
216
217[#807]: https://github.com/lowRISC/opentitan/pull/807
218
219[DESIGN_DELTAS_CAPTURED_IF_ANY]:{{<relref "/doc/project/checklist.md#design-deltas-captured-if-any" >}}
220[ALL_TODOS_RESOLVED]: {{<relref "/doc/project/checklist.md#all-todos-resolved" >}}
221[X_PROP_ANALYSIS_COMPLETED]: {{<relref "/doc/project/checklist.md#x-prop-analysis-completed" >}}
222[NIGHTLY_REGRESSION_AT_100]: {{<relref "/doc/project/checklist.md#nightly-regression-at-100" >}}
223[CODE_COVERAGE_AT_100]: {{<relref "/doc/project/checklist.md#code-coverage-at-100" >}}
224[FUNCTIONAL_COVERAGE_AT_100]: {{<relref "/doc/project/checklist.md#functional-coverage-at-100" >}}
225[NO_ISSUES_PENDING]: {{<relref "/doc/project/checklist.md#no-issues-pending" >}}
226[NO_TOOL_WARNINGS_THROWN]: {{<relref "/doc/project/checklist.md#no-tool-warnings-thrown" >}}
227[PRE_VERIFIED_SUB_MODULES_V3]: {{<relref "/doc/project/checklist.md#pre-verified-sub-modules-v3" >}}
228
Gaurang Chitrodae7e85592019-11-04 18:02:17 -0800[diff] [blame^]229[common_cov_excl.el]:https://github.com/lowRISC/opentitan/blob/9dff09b6c57f4962d67f5f64f8e69ac9bea6885c/hw/dv/tools/vcs/common_cov_excl.el
230[gpio_cov_excl.el]: https://github.com/lowRISC/opentitan/blob/39aaeefdb43661b065c29ceab2efc1065aebf6dd/hw/ip/gpio/dv/cov/gpio_cov_excl.el