| Timothy Trippel | defa5e4 | 2022-08-09 12:13:41 -0700 | [diff] [blame] | 1 | # Copyright lowRISC contributors. |
| 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| 3 | # SPDX-License-Identifier: Apache-2.0 |
| 4 | |
| 5 | name: Chip-Level Test |
| 6 | description: Issue to track the development of a chip-level test. |
| 7 | title: "[chip-test] " |
| 8 | labels: ["Component:ChipLevelTest"] |
| 9 | body: |
| 10 | - type: input |
| 11 | id: name |
| 12 | attributes: |
| 13 | label: Test point name |
| 14 | description: Test point name with link to entry in test plan. |
| 15 | placeholder: > |
| 16 | Example: [chip_sw_uart_tx_rx](https://github.com/lowRISC/opentitan/blob/65e2c995beb96806d13bf04dcd8ef25ca64ac6c5/hw/top_earlgrey/data/chip_testplan.hjson#L24) |
| 17 | validations: |
| 18 | required: true |
| 19 | - type: dropdown |
| 20 | id: host-side-component |
| 21 | attributes: |
| 22 | label: Host side component |
| 23 | description: Does this test require development of a host side component? (In other words, does the test require an external stimulus, like receiving UART or SPI transactions?) |
| 24 | options: |
| Timothy Trippel | b65e270 | 2022-08-09 15:31:46 -0700 | [diff] [blame] | 25 | - None Required |
| Timothy Trippel | defa5e4 | 2022-08-09 12:13:41 -0700 | [diff] [blame] | 26 | - Unknown |
| 27 | - SystemVerilog |
| 28 | - Rust |
| 29 | - SystemVerilog+Rust |
| 30 | - type: dropdown |
| 31 | id: opentitantool-infra-done |
| 32 | attributes: |
| 33 | label: OpenTitanTool infrastructure implemented |
| 34 | description: Does the required opentitantool infrastructure exist so that the Rust component can be developed? If not, this must be developed in SV. 'None' means that there is no Rust component for this test. |
| 35 | options: |
| 36 | - Unknown |
| 37 | - "Yes" |
| 38 | - "No" |
| 39 | - type: input |
| 40 | id: contact |
| 41 | attributes: |
| 42 | label: Contact person |
| 43 | description: GitHub username for a hardware engineer who can answer questions. |
| Michael Munday | a57a1d7 | 2022-08-09 22:15:39 +0100 | [diff] [blame] | 44 | - type: textarea |
| Timothy Trippel | defa5e4 | 2022-08-09 12:13:41 -0700 | [diff] [blame] | 45 | id: checklist |
| 46 | attributes: |
| Michael Munday | a57a1d7 | 2022-08-09 22:15:39 +0100 | [diff] [blame] | 47 | label: Checklist |
| Timothy Trippel | defa5e4 | 2022-08-09 12:13:41 -0700 | [diff] [blame] | 48 | value: | |
| Timothy Trippel | defa5e4 | 2022-08-09 12:13:41 -0700 | [diff] [blame] | 49 | Please fill out this checklist as items are completed. Link to PRs and issues as appropriate. |
| 50 | - [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes) |
| 51 | - [ ] Device-side (C) component developed |
| 52 | - [ ] Bazel build rules developed |
| 53 | - [ ] Host-side component developed |
| 54 | - [ ] HJSON test plan updated with test name (so it shows up in the dashboard) |
| 55 | - [ ] Test added to dvsim nightly regression (and passing at time of checking) |
