blob: 4f4210b11573e55885d2687c25e5a0549f023263 [file] [log] [blame]
Timothy Chencb1293f2019-10-22 12:57:37 -07001// Copyright lowRISC contributors.
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4{
5 name: "riscv_compliance",
6 target_dir: "riscv_compliance",
Timothy Chen49b23b82019-11-07 22:13:02 -08007 patch_dir: "patches/riscv_compliance",
Timothy Chencb1293f2019-10-22 12:57:37 -07008
9 upstream: {
10 url: "https://github.com/riscv/riscv-compliance.git",
11 rev: "master",
12 },
13
14 exclude_from_upstream: [
Timothy Chene13e0f72019-10-22 13:05:33 -070015 "doc",
16 "spec",
Timothy Chencb1293f2019-10-22 12:57:37 -070017 "riscv-ovpsim",
Timothy Chen49b23b82019-11-07 22:13:02 -080018 "riscv-target/Codasip-simulator",
19 "riscv-target/grift",
20 "riscv-target/ibex",
21 "riscv-target/ri5cy",
22 "riscv-target/riscvOVPsim",
23 "riscv-target/rocket",
24 "riscv-target/sail-riscv-c",
25 "riscv-target/sail-riscv-ocaml",
26 "riscv-target/sifive-formal",
27 "riscv-target/spike",
Timothy Chencb1293f2019-10-22 12:57:37 -070028 "riscv-test-suite/rv32mi",
29 "riscv-test-suite/rv32si",
30 "riscv-test-suite/rv32ua",
31 "riscv-test-suite/rv32uc",
32 "riscv-test-suite/rv32ud",
33 "riscv-test-suite/rv32uf",
34 "riscv-test-suite/rv32ui",
35 "riscv-test-suite/rv64i",
36 "riscv-test-suite/rv64im",
Greg Chadwicka23672a2020-04-16 10:16:52 +010037 // FENCE.I test attemps write to flash memory so doesn't work in OT
38 "riscv-test-suite/rv32Zifencei",
Timothy Chencb1293f2019-10-22 12:57:37 -070039 ]
Greg Chadwicka23672a2020-04-16 10:16:52 +010040
41 patch_repo: {
42 url: "https://github.com/lowRISC/riscv-compliance.git",
43 rev_base: "master",
44 rev_patched: "ot",
45 }
Timothy Chencb1293f2019-10-22 12:57:37 -070046}