blob: 3e7143c0e3f8a0205f28c8492acfcbdedd04253d [file] [log] [blame]
Sam Elliott45fb1c62020-06-02 18:18:54 +01001// Copyright lowRISC contributors.
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
Gaurang Chitroda5fd64f52019-10-25 14:21:36 -07004{
5 name: "gpio"
Weicai Yanga0f1ab92020-10-01 17:57:44 -07006 import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
Cindy Chenda227f62021-06-16 10:42:42 -07007 "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
Weicai Yanga0f1ab92020-10-01 17:57:44 -07008 "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
9 "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
Srikrishna Iyera463e172022-02-02 12:09:39 -080010 "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
11 "gpio_sec_cm_testplan.hjson"]
Srikrishna Iyer86169d02021-05-10 09:35:52 -070012 testpoints: [
Gaurang Chitroda5fd64f52019-10-25 14:21:36 -070013 {
Cindy Chena4fcb5a2020-11-11 10:11:49 -080014 name: smoke
15 desc: '''GPIO smoke test that exercises gpio pins as inputs or outputs, and performs
Gaurang Chitroda5fd64f52019-10-25 14:21:36 -070016 data integrity checks by triggering scoreboard checks by reading data_in register.
17 This test repeats following steps are random no. of times:
18 - Configures all gpio pins as inputs, drives random value on cio_gpio_i signal and
19 reads data_in register after random delay
20 - Configures all gpio pins as outputs, programs direct_out and direct_oe registers to
21 random values and reads data_in register after random delay'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070022 stage: V1
Cindy Chena4fcb5a2020-11-11 10:11:49 -080023 tests: ["gpio_smoke",
24 "gpio_smoke_no_pullup_pulldown"]
Gaurang Chitroda5fd64f52019-10-25 14:21:36 -070025 }
26 {
27 name: direct_and_masked_out
28 desc: '''GPIO test that programs `DIRECT_OUT`, `DIRECT_OE`, `MASKED_OUT_LOWER`,
29 `MASKED_OE_LOWER`, `MASKED_OUT_UPPER` and `MASKED_OE_UPPER` registers and checks their
30 effect on GPIO pins as well as DATA_IN register value.
31 Every random iteration in this test would either:
32 - Program one or more of `\*OUT\*` and `\*OE\*` registers, or
33 - Drive new random value on GPIO pins'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070034 stage: V2
Gaurang Chitroda5fd64f52019-10-25 14:21:36 -070035 tests: ["gpio_random_dout_din",
36 "gpio_random_dout_din_no_pullup_pulldown"]
37 }
38 {
39 name: out_in_regs_read_write
40 desc: '''GPIO test that exercises functionality of DATA_OUT and DATA_OE internal registers,
41 and `DATA_IN` register by programming any of `\*OUT\` and `\*OE\*` registers,
42 respectively.
43 Every random iteration in this test would perform one out of following operations:
44 - Drive new random value on GPIO pins
45 - Write random value to any one of `\*OUT\*`, `\*OE\*` or `DATA_IN` registers
46 - Read any one of `\*OUT\*`, `\*OE\*` or `DATA_IN` registers'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070047 stage: V2
Gaurang Chitroda5fd64f52019-10-25 14:21:36 -070048 tests: ["gpio_dout_din_regs_random_rw"]
49 }
50 {
51 name: gpio_interrupt_programming
52 desc: '''GPIO test which programs one or multiple interrupt registers to check GPIO interrupt
53 functionality
54 Every random iteration in this test would do either of following steps, and then read
55 `INTR_STATE` register value:
56 - Drive new random value on GPIO pins (and thereby generate random interrupt event)
57 - Write random value to one or more interrupt registers that include `INTR_ENABLE`,
58 `INTR_CTRL_EN_FALLING`, `INTR_CTRL_EN_LVL_LOW`, `INTR_CTRL_EN_LVL_HIGH` and
59 `INTR_STATE`'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070060 stage: V2
Gaurang Chitroda5fd64f52019-10-25 14:21:36 -070061 tests: ["gpio_intr_rand_pgm"]
62 }
63 {
64 name: random_interrupt_trigger
65 desc: '''GPIO test that randomly generates and clears multiple GPIO interrupts for each
66 random programming of interrupt registers, and performs checks by reading `DATA_IN`
67 and `INTR_STATE` registers.
68 Each random iteration of this test performs following operations:
69 1. Programs one more interrupt registers to random values
70 2. Following two operations are performed in parallel:
71 - Drive random value on GPIO pins multiple times, every time at a random time
72 intervals (random number of clock cycles)
73 - Randomize random time interval (random number of clock cycles) and read either
74 `DATA_IN` or `INTR_STATE` register value at randomized time interval
75 After every read, optionally perform random interrupt clearing operation by
76 writing to `INTR_STATE` register'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070077 stage: V2
Gaurang Chitroda5fd64f52019-10-25 14:21:36 -070078 tests: ["gpio_rand_intr_trigger"]
79 }
80 {
81 name: interrupt_and_noise_filter
82 desc: '''GPIO test that exercise GPIO noise filter functionaliy along with random interrupt
83 programming and randomly toggling each GPIO pin value, independently of other GPIO pins.
84 Each random iteration performs following operations:
85 1. programs random values in one or more interrupt registers
86 2. optionally, programs new random value in `CTRL_EN_INPUT_FILTER` register
87 3. performs following operations in parallel:
88 - drives each GPIO pin independently such that each pin has stable value for random
89 number of clock cycles within the range `[1:FILTER_CYCLES]`, and also predicts
90 updates in values of `DATA_IN` and `INTR_STATE` registers
91 - multiple registers reads, each for either `DATA_IN` or `INTR_STATE`'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070092 stage: V2
Gaurang Chitroda5fd64f52019-10-25 14:21:36 -070093 tests: ["gpio_intr_with_filter_rand_intr_event"]
94 }
95 {
96 name: noise_filter_stress
97 desc: '''GPIO test that stresses noise filter functionality by driving each GPIO pin such
98 independently of other pins, and driving could be either synchronous to clock or
99 asynchronous.
100 Each iteration in test does following:
101 1. Programs one or more interrupt registers with random values
102 2. Programs noise filter register with random value
103 3. Drives each GPIO pin with the mix of both synchronous and asynchronous driving,
104 and each pin is driven independently of others'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700105 stage: V2
Cindy Chen55b97a92020-03-12 10:12:36 -0700106 tests: ["gpio_filter_stress"]
Gaurang Chitroda5fd64f52019-10-25 14:21:36 -0700107 }
108 {
109 name: regs_long_reads_and_writes
110 desc: '''GPIO test that performs back-to-back register writes and back-to-back register reads
111 on randomly selected GPIO registers.
112 Each iteration in this test performs one out of following operations:
113 - Drive new random value on GPIO pins
114 - Perform multiple random writes on randomly selected GPIO registers
115 - Perform multiple random reads on randomly selected GPIO registers'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700116 stage: V2
Gaurang Chitroda5fd64f52019-10-25 14:21:36 -0700117 tests: ["gpio_random_long_reg_writes_reg_reads"]
118 }
119 {
120 name: full_random
121 desc: '''GPIO full random test that performs any of following in each iteration:
122 - Drive new random value on GPIO pins such that GPIO inputs and GPIO outputs shall not
123 result in unknown value on any pin
124 - Write to one or more of `DIRECT_OUT`, `DIRECT_OE`, `MASKED_OUT_UPPER`,
125 `MASKED_OE_UPPER`, `MASKED_OE_LOWER` and `MASKED_OE_LOWER` registers such that GPIO
126 inputs and GPIO outputs shall not result in unknown value on any pin
127 - Write to one or more of GPIO interrupt registers that include `INTR_ENABLE`,
128 `INTR_CTRL_EN_FALLING`, `INTR_CTRL_EN_RISING`, `INTR_CTRL_EN_LVL_HIGH`,
129 `INTR_CTRL_EN_LVL_LOW` and `INTR_STATE`
130 - Write to other GPIO registers `DATA_IN`, `INTR_TEST`, `CTRL_EN_INPUT_FILTER`
131 - Read any one of the GPIO registers
132 - Apply hard reset'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700133 stage: V2
Gaurang Chitroda5fd64f52019-10-25 14:21:36 -0700134 tests: ["gpio_full_random"]
135 }
Cindy Chen55b97a92020-03-12 10:12:36 -0700136 {
137 name: stress_all
138 desc: '''Stress_all test is a random mix of all the test above except csr tests, gpio full
139 random, intr_test and other gpio test that disabled scoreboard'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700140 stage: V2
Cindy Chen55b97a92020-03-12 10:12:36 -0700141 tests: ["gpio_stress_all"]
142 }
Gaurang Chitroda5fd64f52019-10-25 14:21:36 -0700143 ]
144}