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Steve Nelson87a9d122020-10-26 13:10:20 -07001// Copyright lowRISC contributors.
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4{
5 name: "csrng"
Steve Nelson87a9d122020-10-26 13:10:20 -07006 import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
Steve Nelson87a9d122020-10-26 13:10:20 -07007 "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
Steve Nelsonc13ff412020-12-01 14:25:29 -08008 "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
9 "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
Srikrishna Iyera463e172022-02-02 12:09:39 -080010 "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
11 "csrng_sec_cm_testplan.hjson"]
Srikrishna Iyer86169d02021-05-10 09:35:52 -070012 testpoints: [
Steve Nelson87a9d122020-10-26 13:10:20 -070013 {
Cindy Chencb03ee92020-11-11 10:19:14 -080014 name: smoke
Steve Nelson87a9d122020-10-26 13:10:20 -070015 desc: '''
Marno van der Maas0e151552022-11-08 14:27:18 +000016 Verify that sending an instantiate command via the SW path returns OK.
17 Instantiate the CSRNG with flag0 set to true and clen set to 12.
18 Verify that sending a generate command via the SW path returns glen=1 number of words followed by an OK.
Steve Nelson87a9d122020-10-26 13:10:20 -070019 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070020 stage: V1
Cindy Chencb03ee92020-11-11 10:19:14 -080021 tests: ["csrng_smoke"]
Steve Nelson87a9d122020-10-26 13:10:20 -070022 }
23 {
Steve Nelsonc13ff412020-12-01 14:25:29 -080024 name: interrupts
25 desc: '''
Marno van der Maas0e151552022-11-08 14:27:18 +000026 This test verifies the behavior of the Interrupt State Register.
27 Verify cs_cmd_req_done interrupt asserts when glen number of genbit words have been generated.
28 Verify cs_entropy_req interrupt asserts when instantiate or reseed is called with flag0
29 set to false.
30 Verify cs_hw_inst_exc interrupt asserts when any of the application interfaces responds with a CSRNG_ERROR response status signal.
31 Verify cs_fatal_err interrupt asserts when any bit of err_code register is set.
32 Verify that each interrupt clears back to 0 after writing the corresponding interrupt state bit.
Steve Nelsonc13ff412020-12-01 14:25:29 -080033 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070034 stage: V2
Muqing Liu39786f62022-01-09 18:10:54 -080035 tests: ["csrng_intr"]
36 }
37 {
Marno van der Maas0e151552022-11-08 14:27:18 +000038 //TODO For the following untested features add it to the test or create explicit coverpoints in csrng_cmd_cg:
39 //TODO - Invalid MuBi values for flag0 are currently untested.
40 //TODO - Illegal commands are currently untested.
41 //TODO - Fatal alerts are currently untested.
Muqing Liu39786f62022-01-09 18:10:54 -080042 name: alerts
43 desc: '''
Marno van der Maas0e151552022-11-08 14:27:18 +000044 Verify recov_alert asserts when recov_alert_sts becomes non-zero.
45 Verify each respective bit of recov_alert_sts asserts when:
46 - Either of the 3 values in the control register are not valid kMultiBitBool values.
47 - When an initiate or reseed command is sent where flag0 is not a valid kMultiBitBool value.
48 - The genbits bus value is equal to the prior valid value.
49 - When an illegal command is used (0x0,0x6-0xf).
50 Verify that writing zeros to the recoverable alert status register resets all the status bits.
51 Verify fatal_alert asserts when:
52 - An illegal state is reached.
53 - The AES block raises a fatal alert.
54 - There is an integrity failure on the bus (this is covered by an automated test).
Muqing Liu39786f62022-01-09 18:10:54 -080055 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070056 stage: V2
Muqing Liu39786f62022-01-09 18:10:54 -080057 tests: ["csrng_alert"]
58 }
59 {
60 name: err
61 desc: '''
Marno van der Maas0e151552022-11-08 14:27:18 +000062 Verify err_code register bits assert when:
63 - An error has been detected in any of the internal fifos and the corresponding write/read/state bits.
64 - An illegal state is reached in any of the 6 state machines.
65 - An error is detected in the generate command counter.
66 Verify that the err_code register clears all bits after reset.
Muqing Liu39786f62022-01-09 18:10:54 -080067 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070068 stage: V2
Muqing Liu39786f62022-01-09 18:10:54 -080069 tests: ["csrng_err"]
Steve Nelsonc13ff412020-12-01 14:25:29 -080070 }
71 {
Marno van der Maas0e151552022-11-08 14:27:18 +000072 //TODO For the following untested features add it to the test or create explicit coverpoints in csrng_cmd_cg:
73 //TODO - Verification of otp_en_csrng_sw_app_read is currently untested.
74 //TODO - FIPS bit going low from entropy source is currently untested.
Steve Nelsonc13ff412020-12-01 14:25:29 -080075 name: cmds
76 desc: '''
Marno van der Maas0e151552022-11-08 14:27:18 +000077 Verify all csrng commands req/status behave as predicted on all applications: HW0, HW1 and SW.
Steve Nelsonc13ff412020-12-01 14:25:29 -080078 Verify above for all valid values of acmd, clen, flags, glen.
79 Verify for multiple hw app interfaces running in parallel.
Steve Nelsoneea79922021-01-26 06:31:54 -080080 Verify sw/hw app interfaces running in parallel.
Marno van der Maas0e151552022-11-08 14:27:18 +000081 Verify main_sm_state for sw/hw apps.
82 Verify that genbits generates the amount specified by glen.
83 Verify fips bit is set to the inverse of flag0 that was used on the last initialize or reseed.
84 Verify that if otp_en_csrng_sw_app_read is set, genbits and int_state_value registers are readable, and unreadable otherwise.
85 Verify that when AES_HALT is set during a generate command that no request is sent to the AES block.
Steve Nelson544f83e2022-03-30 13:27:31 -070086 Verify commands with continuous/non-continuous valid.
Marno van der Maas0e151552022-11-08 14:27:18 +000087 Verify that if FIPS bit drops at input from entropy source that the generated block also has FIPS low.
Steve Nelsoneea79922021-01-26 06:31:54 -080088 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070089 stage: V2
Steve Nelsonf508d2d2021-12-30 12:04:47 -080090 tests: ["csrng_cmds"]
Steve Nelsoneea79922021-01-26 06:31:54 -080091 }
92 {
93 name: life cycle
94 desc: '''
Steve Nelson544f83e2022-03-30 13:27:31 -070095 Verify lifecycle hardware debug mode.
Marno van der Maas0e151552022-11-08 14:27:18 +000096 When lc_hw_debug_en_i is set to on, the seed from the entropy source must be xor'ed with the diversification value.
Steve Nelsonc13ff412020-12-01 14:25:29 -080097 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070098 stage: V2
Steve Nelson544f83e2022-03-30 13:27:31 -070099 tests: ["csrng_cmds"]
Steve Nelsonc13ff412020-12-01 14:25:29 -0800100 }
101 {
102 name: stress_all
103 desc: '''
Marno van der Maas0e151552022-11-08 14:27:18 +0000104 Combine the other individual testpoints while injecting TL errors and running CSR tests in parallel.
Srikrishna Iyere8713f42021-05-26 20:13:29 -0700105 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700106 stage: V2
Steve Nelsonf508d2d2021-12-30 12:04:47 -0800107 tests: ["csrng_stress_all"]
Steve Nelson87a9d122020-10-26 13:10:20 -0700108 }
109 ]
Muqing Liu39786f62022-01-09 18:10:54 -0800110
111 covergroups: [
112 {
Marno van der Maas0e151552022-11-08 14:27:18 +0000113 //TODO Configuration for enable is currently not covered.
Steve Nelson544f83e2022-03-30 13:27:31 -0700114 name: csrng_cfg_cg
115 desc: '''
116 Covers that all csrng configuration options have been tested.
117 Individual config settings that will be covered include:
118 - otp_en_cs_sw_app_read
119 - sw_app_enable
120 - read_int_state
Marno van der Maas0e151552022-11-08 14:27:18 +0000121 - enable
Marno van der Maas1c8875d2022-11-22 15:35:30 +0000122 - regwen has been true and false
123 - intr_state has had each bit set and unset at least once (handled in comportable ip coverage)
124 Cross:
125 - intr_enable and intr_state (handled in comportable ip coverage)
Steve Nelson544f83e2022-03-30 13:27:31 -0700126 '''
127 }
128 {
129 name: csrng_cmds_cg
130 desc: '''
131 Covers that all csrng commands and variations have been tested for all apps.
132 Individual commands and command options that will be covered include:
133 - app
134 - acmd, clen, flags, glen
Steve Nelson544f83e2022-03-30 13:27:31 -0700135 - continuous/non-continuous valid
Marno van der Maas0e151552022-11-08 14:27:18 +0000136 Crosses of
137 - app/acmd
138 - acmd/clen
139 - acmd/flag0
140 - acmd/glen
141 - For the instantiate and reseed command:
142 - flag0 false and clen 0
143 - flag0 false and clen >0
144 - flag0 true and clen 0
145 - flag0 true and clen >0
146 '''
147 }
148 {
Marno van der Maas1c8875d2022-11-22 15:35:30 +0000149 name: csrng_sts_cg
Marno van der Maas0e151552022-11-08 14:27:18 +0000150 desc: '''
Marno van der Maas1c8875d2022-11-22 15:35:30 +0000151 Covers all possible hw_exc_sts responses from each HW instance and the sub-fields of
152 sw_cmd_sts, which are cmd_rdy and cmd_sts.
Steve Nelson544f83e2022-03-30 13:27:31 -0700153 '''
154 }
155 {
Canberk Topaldd26b242022-11-11 16:57:57 +0000156 name: csrng_err_code_cg
Muqing Liu39786f62022-01-09 18:10:54 -0800157 desc: '''
Marno van der Maas1c8875d2022-11-22 15:35:30 +0000158 Covers all possible fatal errors and possible AES FSM errors inside CSRNG.
Canberk Topaldd26b242022-11-11 16:57:57 +0000159 '''
160 }
161 {
162 name: csrng_err_code_test_cg
163 desc: '''
164 Covers ERR_CODE_TEST register values for setting up fatal errors.
165 '''
166 }
167 {
168 name: csrng_recov_alert_sts_cg
169 desc: '''
170 Covers all possible recoverable alert cases.
Muqing Liu39786f62022-01-09 18:10:54 -0800171 '''
172 }
Canberk Topal6ae00032022-11-16 15:29:37 +0000173 {
174 name: csrng_sfifo_cg
175 desc: '''
176 Covers each app's stage FIFO statuses.
177 - cp_hw0_cmd_depth, cp_hw1_cmd_depth, cp_sw_cmd_depth : Covers current number of commands in FIFO
178 - cp_hw0_genbits_depth, cp_hw1_genbits_depth, cp_sw_genbits_depth : Covers current number of genbit responses in FIFO
179 - cmd_depth_cross : Cross for checking each command FIFO status in different apps
180 - genbits_depth_cross : Cross for checking genbits FIFO status in different apps
Pirmin Vogel7dd9dcc2022-11-21 17:46:32 +0100181 - hw0_cmd_push_cross, hw1_cmd_push_cross, sw_cmd_push_cross : command FIFO fill status x command FIFO write valid x command FIFO write ready
182 - hw0_cmd_pop_cross, hw1_cmd_pop_cross, sw_cmd_pop_cross : command FIFO fill status x command FIFO read ready
183 - hw0_genbits_pop_cross, hw1_genbits_pop_cross, sw_genbits_pop_cross : genbits FIFO fill status x genbits FIFO read valid x genbits FIFO read ready
Canberk Topal6ae00032022-11-16 15:29:37 +0000184 '''
185 }
Muqing Liu39786f62022-01-09 18:10:54 -0800186 ]
Steve Nelson87a9d122020-10-26 13:10:20 -0700187}