| lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 1 | <?xml version="1.0" encoding="UTF-8"?> |
| 2 | <MemInfo Version="1" Minor="0"> |
| 3 | <Processor Endianness="Little" InstPath="dummy"> |
| Timothy Chen | da2e344 | 2020-02-24 21:37:47 -0800 | [diff] [blame] | 4 | <AddressSpace Name="brom" Begin="0" End="4095"> |
| lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 5 | <BusBlock> |
| 6 | <BitLane MemType="RAMB32" Placement="X4Y18"> |
| Timothy Chen | da2e344 | 2020-02-24 21:37:47 -0800 | [diff] [blame] | 7 | <DataWidth MSB="7" LSB="0"/> |
| 8 | <AddressRange Begin="0" End="4095"/> |
| lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 9 | <Parity ON="false" NumBits="0"/> |
| 10 | </BitLane> |
| 11 | <BitLane MemType="RAMB32" Placement="X4Y19"> |
| Timothy Chen | da2e344 | 2020-02-24 21:37:47 -0800 | [diff] [blame] | 12 | <DataWidth MSB="15" LSB="8"/> |
| 13 | <AddressRange Begin="0" End="4095"/> |
| 14 | <Parity ON="false" NumBits="0"/> |
| 15 | </BitLane> |
| 16 | <BitLane MemType="RAMB32" Placement="X3Y14"> |
| 17 | <DataWidth MSB="23" LSB="16"/> |
| 18 | <AddressRange Begin="0" End="4095"/> |
| 19 | <Parity ON="false" NumBits="0"/> |
| 20 | </BitLane> |
| 21 | <BitLane MemType="RAMB32" Placement="X3Y15"> |
| 22 | <DataWidth MSB="31" LSB="24"/> |
| 23 | <AddressRange Begin="0" End="4095"/> |
| lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 24 | <Parity ON="false" NumBits="0"/> |
| 25 | </BitLane> |
| 26 | </BusBlock> |
| 27 | </AddressSpace> |
| 28 | </Processor> |
| 29 | <Config> |
| 30 | <Option Name="Part" Val="xc7a200tsbg484-1"/> |
| 31 | </Config> |
| 32 | </MemInfo> |
