Timothy Chen | cb1293f | 2019-10-22 12:57:37 -0700 | [diff] [blame] | 1 | // Copyright lowRISC contributors. |
| 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| 3 | // SPDX-License-Identifier: Apache-2.0 |
| 4 | { |
| 5 | name: "riscv_compliance", |
| 6 | target_dir: "riscv_compliance", |
Timothy Chen | 49b23b8 | 2019-11-07 22:13:02 -0800 | [diff] [blame] | 7 | patch_dir: "patches/riscv_compliance", |
Timothy Chen | cb1293f | 2019-10-22 12:57:37 -0700 | [diff] [blame] | 8 | |
| 9 | upstream: { |
| 10 | url: "https://github.com/riscv/riscv-compliance.git", |
| 11 | rev: "master", |
| 12 | }, |
| 13 | |
| 14 | exclude_from_upstream: [ |
Timothy Chen | e13e0f7 | 2019-10-22 13:05:33 -0700 | [diff] [blame] | 15 | "doc", |
| 16 | "spec", |
Timothy Chen | cb1293f | 2019-10-22 12:57:37 -0700 | [diff] [blame] | 17 | "riscv-ovpsim", |
Timothy Chen | 49b23b8 | 2019-11-07 22:13:02 -0800 | [diff] [blame] | 18 | "riscv-target/Codasip-simulator", |
| 19 | "riscv-target/grift", |
| 20 | "riscv-target/ibex", |
| 21 | "riscv-target/ri5cy", |
| 22 | "riscv-target/riscvOVPsim", |
| 23 | "riscv-target/rocket", |
| 24 | "riscv-target/sail-riscv-c", |
| 25 | "riscv-target/sail-riscv-ocaml", |
| 26 | "riscv-target/sifive-formal", |
| 27 | "riscv-target/spike", |
Timothy Chen | cb1293f | 2019-10-22 12:57:37 -0700 | [diff] [blame] | 28 | "riscv-test-suite/rv32mi", |
| 29 | "riscv-test-suite/rv32si", |
| 30 | "riscv-test-suite/rv32ua", |
| 31 | "riscv-test-suite/rv32uc", |
| 32 | "riscv-test-suite/rv32ud", |
| 33 | "riscv-test-suite/rv32uf", |
| 34 | "riscv-test-suite/rv32ui", |
| 35 | "riscv-test-suite/rv64i", |
| 36 | "riscv-test-suite/rv64im", |
| 37 | ] |
| 38 | } |