Blame - hw/ip/sysrst_ctrl/doc/checklist.md - 3p/lowrisc/opentitan

2021-06-23 11:27:41 -0700

[diff] [blame]

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---

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title: "SYSRST_CTRL Checklist"

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---

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This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [SYSRST_CTRL peripheral.]({{< relref "." >}})

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All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})

## Design Checklist

### D1

Type | Item | Resolution | Note/Collaterals

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--------------|--------------------------------|-------------|------------------

Michael Schaffner

2021-06-23 11:28:05 -0700

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Documentation | [SPEC_COMPLETE][] | Done | [SYSRST_CTRL Design Spec]({{<relref "." >}})

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Documentation | [CSR_DEFINED][] | Done |

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RTL | [CLKRST_CONNECTED][] | Done |

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RTL | [IP_TOP][] | Done |

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RTL | [IP_INSTANTIABLE][] | Done |

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RTL | [PHYSICAL_MACROS_DEFINED_80][] | N/A |

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RTL | [FUNC_IMPLEMENTED][] | Done |

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RTL | [ASSERT_KNOWN_ADDED][] | Done |

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Code Quality | [LINT_SETUP][] | Done |

Michael Schaffner

2021-06-23 11:27:41 -0700

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[SPEC_COMPLETE]: {{<relref "/doc/project/checklist.md#spec_complete" >}}

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[CSR_DEFINED]: {{<relref "/doc/project/checklist.md#csr_defined" >}}

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[CLKRST_CONNECTED]: {{<relref "/doc/project/checklist.md#clkrst_connected" >}}

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[IP_TOP]: {{<relref "/doc/project/checklist.md#ip_top" >}}

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[IP_INSTANTIABLE]: {{<relref "/doc/project/checklist.md#ip_instantiable" >}}

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[PHYSICAL_MACROS_DEFINED_80]: {{<relref "/doc/project/checklist.md#physical_macros_defined_80" >}}

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[FUNC_IMPLEMENTED]: {{<relref "/doc/project/checklist.md#func_implemented" >}}

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[ASSERT_KNOWN_ADDED]: {{<relref "/doc/project/checklist.md#assert_known_added" >}}

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[LINT_SETUP]: {{<relref "/doc/project/checklist.md#lint_setup" >}}

### D2

Type | Item | Resolution | Note/Collaterals

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--------------|-------------------------|-------------|------------------

Michael Schaffner

2021-06-23 11:28:05 -0700

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Documentation | [NEW_FEATURES][] | Done |

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Documentation | [BLOCK_DIAGRAM][] | Done |

Michael Schaffner

8aa911c

2021-08-12 18:10:19 -0700

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Documentation | [DOC_INTERFACE][] | Done |

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Documentation | [MISSING_FUNC][] | Done |

Michael Schaffner

2021-06-23 11:28:05 -0700

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Documentation | [FEATURE_FROZEN][] | Done |

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RTL | [FEATURE_COMPLETE][] | Done |

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RTL | [AREA_CHECK][] | Done |

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RTL | [PORT_FROZEN][] | Done |

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RTL | [ARCHITECTURE_FROZEN][] | Done |

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RTL | [REVIEW_TODO][] | Done |

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RTL | [STYLE_X][] | Done |

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Code Quality | [LINT_PASS][] | Done |

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Code Quality | [CDC_SETUP][] | Waived | CDC tool setup not yet available.

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Code Quality | [FPGA_TIMING][] | Done |

Michael Schaffner

8aa911c

2021-08-12 18:10:19 -0700

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Code Quality | [CDC_SYNCMACRO][] | Done |

Tom Roberts

afb72b5

2021-09-07 15:32:55 +0100

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Security | [SEC_CM_DOCUMENTED][] | N/A |

Michael Schaffner

2021-06-23 11:28:05 -0700

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Security | [SEC_RND_CNST][] | N/A |

Michael Schaffner

2021-06-23 11:27:41 -0700

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[NEW_FEATURES]: {{<relref "/doc/project/checklist.md#new_features" >}}

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[BLOCK_DIAGRAM]: {{<relref "/doc/project/checklist.md#block_diagram" >}}

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[DOC_INTERFACE]: {{<relref "/doc/project/checklist.md#doc_interface" >}}

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[MISSING_FUNC]: {{<relref "/doc/project/checklist.md#missing_func" >}}

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[FEATURE_FROZEN]: {{<relref "/doc/project/checklist.md#feature_frozen" >}}

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[FEATURE_COMPLETE]: {{<relref "/doc/project/checklist.md#feature_complete" >}}

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[AREA_CHECK]: {{<relref "/doc/project/checklist.md#area_check" >}}

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[PORT_FROZEN]: {{<relref "/doc/project/checklist.md#port_frozen" >}}

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[ARCHITECTURE_FROZEN]: {{<relref "/doc/project/checklist.md#architecture_frozen" >}}

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[REVIEW_TODO]: {{<relref "/doc/project/checklist.md#review_todo" >}}

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[STYLE_X]: {{<relref "/doc/project/checklist.md#style_x" >}}

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[LINT_PASS]: {{<relref "/doc/project/checklist.md#lint_pass" >}}

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[CDC_SETUP]: {{<relref "/doc/project/checklist.md#cdc_setup" >}}

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[FPGA_TIMING]: {{<relref "/doc/project/checklist.md#fpga_timing" >}}

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[CDC_SYNCMACRO]: {{<relref "/doc/project/checklist.md#cdc_syncmacro" >}}

Tom Roberts

afb72b5

2021-09-07 15:32:55 +0100

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[SEC_CM_DOCUMENTED]: {{<relref "/doc/project/checklist.md#sec_cm_documented" >}}

Michael Schaffner

2021-06-23 11:27:41 -0700

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[SEC_RND_CNST]: {{<relref "/doc/project/checklist.md#sec_rnd_cnst" >}}

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Michael Schaffner

2021-11-04 15:58:58 -0700

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### D2S

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Michael Schaffner

87c4100

2021-12-10 14:29:01 -0800

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Type | Item | Resolution | Note/Collaterals

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--------------|------------------------------|-------------|------------------

Michael Schaffner

c107a19

2022-01-25 20:54:50 -0800

[diff] [blame]

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Security | [SEC_CM_ASSETS_LISTED][] | Done |

Srikrishna Iyer

2022-02-08 21:17:20 -0800

[diff] [blame]

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Security | [SEC_CM_IMPLEMENTED][] | Done |

Michael Schaffner

2022-04-25 17:43:12 -0700

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Security | [SEC_CM_NON_RESET_FLOPS][] | N/A |

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Security | [SEC_CM_SHADOW_REGS][] | N/A |

Michael Schaffner

c107a19

2022-01-25 20:54:50 -0800

[diff] [blame]

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Security | [SEC_CM_RTL_REVIEWED][] | N/A |

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Security | [SEC_CM_COUNCIL_REVIEWED][] | N/A | This block only contains the bus-integrity CM.

Michael Schaffner

2021-11-04 15:58:58 -0700

[diff] [blame]

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Michael Schaffner

87c4100

2021-12-10 14:29:01 -0800

[diff] [blame]

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[SEC_CM_ASSETS_LISTED]: {{<relref "/doc/project/checklist.md#sec_cm_assets_listed" >}}

Michael Schaffner

ec66fc8

2022-01-18 10:14:16 -0800

[diff] [blame]

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[SEC_CM_IMPLEMENTED]: {{<relref "/doc/project/checklist.md#sec_cm_implemented" >}}

Michael Schaffner

2022-04-25 17:43:12 -0700

[diff] [blame]

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[SEC_CM_NON_RESET_FLOPS]: {{<relref "/doc/project/checklist.md#sec_cm_non_reset_flops" >}}

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[SEC_CM_SHADOW_REGS]: {{<relref "/doc/project/checklist.md#sec_cm_shadow_regs" >}}

Michael Schaffner

87c4100

2021-12-10 14:29:01 -0800

[diff] [blame]

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[SEC_CM_RTL_REVIEWED]: {{<relref "/doc/project/checklist.md#sec_cm_rtl_reviewed" >}}

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[SEC_CM_COUNCIL_REVIEWED]: {{<relref "/doc/project/checklist.md#sec_cm_council_reviewed" >}}

Michael Schaffner

2021-11-04 15:58:58 -0700

[diff] [blame]

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Michael Schaffner

2021-06-23 11:27:41 -0700

[diff] [blame]

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### D3

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Type | Item | Resolution | Note/Collaterals

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--------------|-------------------------|-------------|------------------

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Documentation | [NEW_FEATURES_D3][] | Not Started |

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RTL | [TODO_COMPLETE][] | Not Started |

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Code Quality | [LINT_COMPLETE][] | Not Started |

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Code Quality | [CDC_COMPLETE][] | Not Started |

Michael Schaffner

2022-04-25 17:43:12 -0700

[diff] [blame]

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Code Quality | [RDC_COMPLETE][] | Not Started |

Michael Schaffner

2021-06-23 11:27:41 -0700

[diff] [blame]

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Review | [REVIEW_RTL][] | Not Started |

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Review | [REVIEW_DELETED_FF][] | Not Started |

Michael Schaffner

2021-06-23 11:27:41 -0700

[diff] [blame]

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Review | [REVIEW_SW_CHANGE][] | Not Started |

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Review | [REVIEW_SW_ERRATA][] | Not Started |

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Review | Reviewer(s) | Not Started |

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Review | Signoff date | Not Started |

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[NEW_FEATURES_D3]: {{<relref "/doc/project/checklist.md#new_features_d3" >}}

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[TODO_COMPLETE]: {{<relref "/doc/project/checklist.md#todo_complete" >}}

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[LINT_COMPLETE]: {{<relref "/doc/project/checklist.md#lint_complete" >}}

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[CDC_COMPLETE]: {{<relref "/doc/project/checklist.md#cdc_complete" >}}

Michael Schaffner

2022-04-25 17:43:12 -0700

[diff] [blame]

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[RDC_COMPLETE]: {{<relref "/doc/project/checklist.md#rdc_complete" >}}

Michael Schaffner

2021-06-23 11:27:41 -0700

[diff] [blame]

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[REVIEW_RTL]: {{<relref "/doc/project/checklist.md#review_rtl" >}}

Michael Schaffner

2021-06-23 11:27:41 -0700

[diff] [blame]

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[REVIEW_DELETED_FF]: {{<relref "/doc/project/checklist.md#review_deleted_ff" >}}

Michael Schaffner

2021-06-23 11:27:41 -0700

[diff] [blame]

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[REVIEW_SW_CHANGE]: {{<relref "/doc/project/checklist.md#review_sw_change" >}}

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[REVIEW_SW_ERRATA]: {{<relref "/doc/project/checklist.md#review_sw_errata" >}}

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## Verification Checklist

### V1

Madhuri Patel

2022-01-20 17:01:24 +0000

[diff] [blame]

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Type | Item | Resolution | Note/Collaterals

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--------------|---------------------------------------|------------|------------------

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Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done |({{<relref "dv/index.md" >}})

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Documentation | [TESTPLAN_COMPLETED][] | Done |({{<relref "dv/index.md#testplan" >}})

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Testbench | [TB_TOP_CREATED][] | Done |

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Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |

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Testbench | [SIM_TB_ENV_CREATED][] | Done |

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Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Done |

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Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done |

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Testbench | [TB_GEN_AUTOMATED][] | Done |

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Tests | [SIM_SMOKE_TEST_PASSING][] | Done |

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Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Done |

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Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | N/A |

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Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done |

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Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Done |

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Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Done |

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Regression | [FPV_REGRESSION_SETUP][] | N/A |

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Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Done |

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Code Quality | [TB_LINT_SETUP][] | Done |

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Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Done |

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Review | [DESIGN_SPEC_REVIEWED][] | Done |

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Review | [TESTPLAN_REVIEWED][] | Done |

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Review | [STD_TEST_CATEGORIES_PLANNED][] | Done |

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Review | [V2_CHECKLIST_SCOPED][] | Done |

Michael Schaffner

2021-06-23 11:27:41 -0700

[diff] [blame]

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[DV_DOC_DRAFT_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_doc_draft_completed" >}}

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[TESTPLAN_COMPLETED]: {{<relref "/doc/project/checklist.md#testplan_completed" >}}

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[TB_TOP_CREATED]: {{<relref "/doc/project/checklist.md#tb_top_created" >}}

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[PRELIMINARY_ASSERTION_CHECKS_ADDED]: {{<relref "/doc/project/checklist.md#preliminary_assertion_checks_added" >}}

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[SIM_TB_ENV_CREATED]: {{<relref "/doc/project/checklist.md#sim_tb_env_created" >}}

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[SIM_RAL_MODEL_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#sim_ral_model_gen_automated" >}}

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[CSR_CHECK_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#csr_check_gen_automated" >}}

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[TB_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#tb_gen_automated" >}}

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[SIM_SMOKE_TEST_PASSING]: {{<relref "/doc/project/checklist.md#sim_smoke_test_passing" >}}

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[SIM_CSR_MEM_TEST_SUITE_PASSING]: {{<relref "/doc/project/checklist.md#sim_csr_mem_test_suite_passing" >}}

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[FPV_MAIN_ASSERTIONS_PROVEN]: {{<relref "/doc/project/checklist.md#fpv_main_assertions_proven" >}}

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[SIM_ALT_TOOL_SETUP]: {{<relref "/doc/project/checklist.md#sim_alt_tool_setup" >}}

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[SIM_SMOKE_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#sim_smoke_regression_setup" >}}

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[SIM_NIGHTLY_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#sim_nightly_regression_setup" >}}

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[FPV_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#fpv_regression_setup" >}}

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[SIM_COVERAGE_MODEL_ADDED]: {{<relref "/doc/project/checklist.md#sim_coverage_model_added" >}}

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[TB_LINT_SETUP]: {{<relref "/doc/project/checklist.md#tb_lint_setup" >}}

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[PRE_VERIFIED_SUB_MODULES_V1]: {{<relref "/doc/project/checklist.md#pre_verified_sub_modules_v1" >}}

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[DESIGN_SPEC_REVIEWED]: {{<relref "/doc/project/checklist.md#design_spec_reviewed" >}}

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[TESTPLAN_REVIEWED]: {{<relref "/doc/project/checklist.md#testplan_reviewed" >}}

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[STD_TEST_CATEGORIES_PLANNED]: {{<relref "/doc/project/checklist.md#std_test_categories_planned" >}}

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[V2_CHECKLIST_SCOPED]: {{<relref "/doc/project/checklist.md#v2_checklist_scoped" >}}

### V2

Type | Item | Resolution | Note/Collaterals

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--------------|-----------------------------------------|-------------|------------------

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Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Not Started |

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Documentation | [DV_DOC_COMPLETED][] | Not Started |

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Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Not Started |

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Testbench | [ALL_INTERFACES_EXERCISED][] | Not Started |

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Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Not Started |

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Testbench | [SIM_TB_ENV_COMPLETED][] | Not Started |

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Tests | [SIM_ALL_TESTS_PASSING][] | Not Started |

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Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | Not Started |

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Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | Not Started |

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Tests | [SIM_FW_SIMULATED][] | Not Started |

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Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Not Started |

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Coverage | [SIM_CODE_COVERAGE_V2][] | Not Started |

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Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Not Started |

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Coverage | [FPV_CODE_COVERAGE_V2][] | Not Started |

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Coverage | [FPV_COI_COVERAGE_V2][] | Not Started |

Michael Schaffner

2021-06-23 11:27:41 -0700

[diff] [blame]

189

Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Not Started |

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Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Not Started |

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Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Not Started |

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Review | [DV_DOC_TESTPLAN_REVIEWED][] | Not Started |

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Review | [V3_CHECKLIST_SCOPED][] | Not Started |

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[DESIGN_DELTAS_CAPTURED_V2]: {{<relref "/doc/project/checklist.md#design_deltas_captured_v2" >}}

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[DV_DOC_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_doc_completed" >}}

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[FUNCTIONAL_COVERAGE_IMPLEMENTED]: {{<relref "/doc/project/checklist.md#functional_coverage_implemented" >}}

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[ALL_INTERFACES_EXERCISED]: {{<relref "/doc/project/checklist.md#all_interfaces_exercised" >}}

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[ALL_ASSERTION_CHECKS_ADDED]: {{<relref "/doc/project/checklist.md#all_assertion_checks_added" >}}

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[SIM_TB_ENV_COMPLETED]: {{<relref "/doc/project/checklist.md#sim_tb_env_completed" >}}

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[SIM_ALL_TESTS_PASSING]: {{<relref "/doc/project/checklist.md#sim_all_tests_passing" >}}

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[FPV_ALL_ASSERTIONS_WRITTEN]: {{<relref "/doc/project/checklist.md#fpv_all_assertions_written" >}}

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[FPV_ALL_ASSUMPTIONS_REVIEWED]: {{<relref "/doc/project/checklist.md#fpv_all_assumptions_reviewed" >}}

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[SIM_FW_SIMULATED]: {{<relref "/doc/project/checklist.md#sim_fw_simulated" >}}

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[SIM_NIGHTLY_REGRESSION_V2]: {{<relref "/doc/project/checklist.md#sim_nightly_regression_v2" >}}

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[SIM_CODE_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#sim_code_coverage_v2" >}}

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[SIM_FUNCTIONAL_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#sim_functional_coverage_v2" >}}

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[FPV_CODE_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#fpv_code_coverage_v2" >}}

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[FPV_COI_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#fpv_coi_coverage_v2" >}}

Michael Schaffner

2021-06-23 11:27:41 -0700

[diff] [blame]

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[PRE_VERIFIED_SUB_MODULES_V2]: {{<relref "/doc/project/checklist.md#pre_verified_sub_modules_v2" >}}

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[NO_HIGH_PRIORITY_ISSUES_PENDING]: {{<relref "/doc/project/checklist.md#no_high_priority_issues_pending" >}}

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[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:{{<relref "/doc/project/checklist.md#all_low_priority_issues_root_caused" >}}

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[DV_DOC_TESTPLAN_REVIEWED]: {{<relref "/doc/project/checklist.md#dv_doc_testplan_reviewed" >}}

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[V3_CHECKLIST_SCOPED]: {{<relref "/doc/project/checklist.md#v3_checklist_scoped" >}}

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Michael Schaffner

2021-11-04 15:58:58 -0700

[diff] [blame]

216

### V2S

217

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Type | Item | Resolution | Note/Collaterals

219

--------------|-----------------------------------------|-------------|------------------

Srikrishna Iyer

2022-02-08 21:17:20 -0800

[diff] [blame]

220

Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Not Started |

Weicai Yang

6a25a62

2022-02-02 11:54:22 -0800

[diff] [blame]

221

Tests | [FPV_SEC_CM_VERIFIED][] | Not Started |

222

Tests | [SIM_SEC_CM_VERIFIED][] | Not Started |

Weicai Yang

e5b4eda

2022-03-08 15:51:00 -0800

[diff] [blame]

223

Coverage | [SIM_COVERAGE_REVIEWED][] | Not Started |

Srikrishna Iyer

2022-02-08 21:17:20 -0800

[diff] [blame]

224

Review | [SEC_CM_DV_REVIEWED][] | Not Started |

225

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[SEC_CM_TESTPLAN_COMPLETED]: {{<relref "/doc/project/checklist.md#sec_cm_testplan_completed" >}}

Weicai Yang

6a25a62

2022-02-02 11:54:22 -0800

[diff] [blame]

227

[FPV_SEC_CM_VERIFIED]: {{<relref "/doc/project/checklist.md#fpv_sec_cm_verified" >}}

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[SIM_SEC_CM_VERIFIED]: {{<relref "/doc/project/checklist.md#sim_sec_cm_verified" >}}

Weicai Yang

e5b4eda

2022-03-08 15:51:00 -0800

[diff] [blame]

229

[SIM_COVERAGE_REVIEWED]: {{<relref "/doc/project/checklist.md#sim_coverage_reviewed" >}}

Srikrishna Iyer

2022-02-08 21:17:20 -0800

[diff] [blame]

230

[SEC_CM_DV_REVIEWED]: {{<relref "/doc/project/checklist.md#sec_cm_dv_reviewed" >}}

Michael Schaffner

2021-11-04 15:58:58 -0700

[diff] [blame]

231

Michael Schaffner