Blame - util/uvmdvgen/checklist.md.tpl - 3p/lowrisc/opentitan

2019-10-28 23:23:40 -0700

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Philipp Wagner

2020-09-17 10:48:36 +0100

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<%text>## Design Checklist</%text>

Eunchan Kim

2019-10-28 23:23:40 -0700

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Philipp Wagner

2020-09-17 10:48:36 +0100

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15

<%text>### D1</%text>

Eunchan Kim

2019-10-28 23:23:40 -0700

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Scott Johnson

1fba155

2020-10-12 23:18:58 -0700

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Type | Item | Resolution | Note/Collaterals

18

--------------|--------------------------------|-------------|------------------

Philipp Wagner

5bf19db

2021-03-18 15:40:08 +0000

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Documentation | [SPEC_COMPLETE][] | Not Started | [${name.upper()} Design Spec]({{<relref "." >}})

Scott Johnson

1fba155

2020-10-12 23:18:58 -0700

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20

Documentation | [CSR_DEFINED][] | Not Started |

21

RTL | [CLKRST_CONNECTED][] | Not Started |

22

RTL | [IP_TOP][] | Not Started |

23

RTL | [IP_INSTANTIABLE][] | Not Started |

24

RTL | [PHYSICAL_MACROS_DEFINED_80][] | Not Started |

25

RTL | [FUNC_IMPLEMENTED][] | Not Started |

26

RTL | [ASSERT_KNOWN_ADDED][] | Not Started |

27

Code Quality | [LINT_SETUP][] | Not Started |

Eunchan Kim

2019-10-28 23:23:40 -0700

[diff] [blame]

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Scott Johnson

1fba155

2020-10-12 23:18:58 -0700

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[SPEC_COMPLETE]: {{<relref "/doc/project/checklist.md#spec_complete" >}}

30

[CSR_DEFINED]: {{<relref "/doc/project/checklist.md#csr_defined" >}}

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[CLKRST_CONNECTED]: {{<relref "/doc/project/checklist.md#clkrst_connected" >}}

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[IP_TOP]: {{<relref "/doc/project/checklist.md#ip_top" >}}

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[IP_INSTANTIABLE]: {{<relref "/doc/project/checklist.md#ip_instantiable" >}}

34

[PHYSICAL_MACROS_DEFINED_80]: {{<relref "/doc/project/checklist.md#physical_macros_defined_80" >}}

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[FUNC_IMPLEMENTED]: {{<relref "/doc/project/checklist.md#func_implemented" >}}

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[ASSERT_KNOWN_ADDED]: {{<relref "/doc/project/checklist.md#assert_known_added" >}}

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[LINT_SETUP]: {{<relref "/doc/project/checklist.md#lint_setup" >}}

Eunchan Kim

2019-10-28 23:23:40 -0700

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38

Philipp Wagner

2020-09-17 10:48:36 +0100

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<%text>### D2</%text>

Eunchan Kim

2019-10-28 23:23:40 -0700

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Type | Item | Resolution | Note/Collaterals

42

--------------|-------------------------|-------------|------------------

Scott Johnson

8573fa2

2019-11-01 14:49:56 -0700

[diff] [blame]

43

Documentation | [NEW_FEATURES][] | Not Started |

Eunchan Kim

2019-10-28 23:23:40 -0700

[diff] [blame]

44

Documentation | [BLOCK_DIAGRAM][] | Not Started |

45

Documentation | [DOC_INTERFACE][] | Not Started |

46

Documentation | [MISSING_FUNC][] | Not Started |

47

Documentation | [FEATURE_FROZEN][] | Not Started |

48

RTL | [FEATURE_COMPLETE][] | Not Started |

Cindy Chen

432430e

2020-11-12 09:51:50 -0800

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49

RTL | [AREA_CHECK][] | Not Started |

Eunchan Kim

2019-10-28 23:23:40 -0700

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50

RTL | [PORT_FROZEN][] | Not Started |

51

RTL | [ARCHITECTURE_FROZEN][] | Not Started |

52

RTL | [REVIEW_TODO][] | Not Started |

53

RTL | [STYLE_X][] | Not Started |

54

Code Quality | [LINT_PASS][] | Not Started |

55

Code Quality | [CDC_SETUP][] | Not Started |

56

Code Quality | [FPGA_TIMING][] | Not Started |

57

Code Quality | [CDC_SYNCMACRO][] | Not Started |

Tom Roberts

2021-09-07 15:32:55 +0100

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58

Security | [SEC_CM_DOCUMENTED][] | Not Started |

Michael Schaffner

e80c0c4

2020-11-03 14:48:57 -0800

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59

Security | [SEC_RND_CNST][] | Not Started |

Eunchan Kim

2019-10-28 23:23:40 -0700

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Michael Schaffner

2020-10-09 19:20:39 -0700

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[NEW_FEATURES]: {{<relref "/doc/project/checklist.md#new_features" >}}

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[BLOCK_DIAGRAM]: {{<relref "/doc/project/checklist.md#block_diagram" >}}

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[DOC_INTERFACE]: {{<relref "/doc/project/checklist.md#doc_interface" >}}

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[MISSING_FUNC]: {{<relref "/doc/project/checklist.md#missing_func" >}}

65

[FEATURE_FROZEN]: {{<relref "/doc/project/checklist.md#feature_frozen" >}}

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[FEATURE_COMPLETE]: {{<relref "/doc/project/checklist.md#feature_complete" >}}

Cindy Chen

432430e

2020-11-12 09:51:50 -0800

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67

[AREA_CHECK]: {{<relref "/doc/project/checklist.md#area_check" >}}

Michael Schaffner

2020-10-09 19:20:39 -0700

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[PORT_FROZEN]: {{<relref "/doc/project/checklist.md#port_frozen" >}}

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[ARCHITECTURE_FROZEN]: {{<relref "/doc/project/checklist.md#architecture_frozen" >}}

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[REVIEW_TODO]: {{<relref "/doc/project/checklist.md#review_todo" >}}

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[STYLE_X]: {{<relref "/doc/project/checklist.md#style_x" >}}

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[LINT_PASS]: {{<relref "/doc/project/checklist.md#lint_pass" >}}

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[CDC_SETUP]: {{<relref "/doc/project/checklist.md#cdc_setup" >}}

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[FPGA_TIMING]: {{<relref "/doc/project/checklist.md#fpga_timing" >}}

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[CDC_SYNCMACRO]: {{<relref "/doc/project/checklist.md#cdc_syncmacro" >}}

Tom Roberts

2021-09-07 15:32:55 +0100

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[SEC_CM_DOCUMENTED]: {{<relref "/doc/project/checklist.md#sec_cm_documented" >}}

Michael Schaffner

e80c0c4

2020-11-03 14:48:57 -0800

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[SEC_RND_CNST]: {{<relref "/doc/project/checklist.md#sec_rnd_cnst" >}}

Eunchan Kim

2019-10-28 23:23:40 -0700

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Michael Schaffner

2021-11-04 15:58:58 -0700

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<%text>### D2S</%text>

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Michael Schaffner

2021-12-10 14:26:30 -0800

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Type | Item | Resolution | Note/Collaterals

82

--------------|------------------------------|-------------|------------------

Michael Schaffner

2021-12-10 14:26:30 -0800

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83

Security | [SEC_CM_ASSETS_LISTED][] | Not Started |

Michael Schaffner

ec66fc8

2022-01-18 10:14:16 -0800

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84

Security | [SEC_CM_IMPLEMENTED][] | Not Started |

Michael Schaffner

2021-12-10 14:26:30 -0800

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85

Security | [SEC_CM_RTL_REVIEWED][] | Not Started |

86

Security | [SEC_CM_COUNCIL_REVIEWED][] | Not Started |

Michael Schaffner

2021-11-04 15:58:58 -0700

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Michael Schaffner

2021-12-10 14:26:30 -0800

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[SEC_CM_ASSETS_LISTED]: {{<relref "/doc/project/checklist.md#sec_cm_assets_listed" >}}

Michael Schaffner

ec66fc8

2022-01-18 10:14:16 -0800

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[SEC_CM_IMPLEMENTED]: {{<relref "/doc/project/checklist.md#sec_cm_implemented" >}}

Michael Schaffner

2021-12-10 14:26:30 -0800

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[SEC_CM_RTL_REVIEWED]: {{<relref "/doc/project/checklist.md#sec_cm_rtl_reviewed" >}}

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[SEC_CM_COUNCIL_REVIEWED]: {{<relref "/doc/project/checklist.md#sec_cm_council_reviewed" >}}

Michael Schaffner

2021-11-04 15:58:58 -0700

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92

Philipp Wagner

2020-09-17 10:48:36 +0100

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93

<%text>### D3</%text>

Eunchan Kim

2019-10-28 23:23:40 -0700

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Type | Item | Resolution | Note/Collaterals

96

--------------|-------------------------|-------------|------------------

97

Documentation | [NEW_FEATURES_D3][] | Not Started |

98

RTL | [TODO_COMPLETE][] | Not Started |

99

Code Quality | [LINT_COMPLETE][] | Not Started |

100

Code Quality | [CDC_COMPLETE][] | Not Started |

101

Review | [REVIEW_RTL][] | Not Started |

102

Review | [REVIEW_DELETED_FF][] | Not Started |

103

Review | [REVIEW_SW_CSR][] | Not Started |

104

Review | [REVIEW_SW_FATAL_ERR][] | Not Started |

105

Review | [REVIEW_SW_CHANGE][] | Not Started |

106

Review | [REVIEW_SW_ERRATA][] | Not Started |

Tom Roberts

2021-09-07 15:32:55 +0100

[diff] [blame]

107

Security | [SEC_NON_RESET_FLOPS][] | Not Started |

108

Security | [SEC_SHADOW_REGS][] | Not Started |

Eunchan Kim

2019-10-28 23:23:40 -0700

[diff] [blame]

109

Review | Reviewer(s) | Not Started |

110

Review | Signoff date | Not Started |

111

Michael Schaffner

2020-10-09 19:20:39 -0700

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[NEW_FEATURES_D3]: {{<relref "/doc/project/checklist.md#new_features_d3" >}}

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[TODO_COMPLETE]: {{<relref "/doc/project/checklist.md#todo_complete" >}}

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[LINT_COMPLETE]: {{<relref "/doc/project/checklist.md#lint_complete" >}}

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[CDC_COMPLETE]: {{<relref "/doc/project/checklist.md#cdc_complete" >}}

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[REVIEW_RTL]: {{<relref "/doc/project/checklist.md#review_rtl" >}}

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[REVIEW_DBG]: {{<relref "/doc/project/checklist.md#review_dbg" >}}

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[REVIEW_DELETED_FF]: {{<relref "/doc/project/checklist.md#review_deleted_ff" >}}

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[REVIEW_SW_CSR]: {{<relref "/doc/project/checklist.md#review_sw_csr" >}}

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[REVIEW_SW_FATAL_ERR]: {{<relref "/doc/project/checklist.md#review_sw_fatal_err" >}}

121

[REVIEW_SW_CHANGE]: {{<relref "/doc/project/checklist.md#review_sw_change" >}}

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[REVIEW_SW_ERRATA]: {{<relref "/doc/project/checklist.md#review_sw_errata" >}}

Tom Roberts

2021-09-07 15:32:55 +0100

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123

[SEC_NON_RESET_FLOPS]: {{<relref "/doc/project/checklist.md#sec_non_reset_flops" >}}

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[SEC_SHADOW_REGS]: {{<relref "/doc/project/checklist.md#sec_shadow_regs" >}}

Eunchan Kim

2019-10-28 23:23:40 -0700

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125

Philipp Wagner

2020-09-17 10:48:36 +0100

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126

<%text>## Verification Checklist</%text>

Eunchan Kim

2019-10-28 23:23:40 -0700

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127

Philipp Wagner

2020-09-17 10:48:36 +0100

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128

<%text>### V1</%text>

Eunchan Kim

2019-10-28 23:23:40 -0700

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Type | Item | Resolution | Note/Collaterals

131

--------------|---------------------------------------|-------------|------------------

Srikrishna Iyer

2021-05-14 14:26:53 -0700

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132

Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [${name.upper()} DV document]({{<relref "dv" >}})

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Documentation | [TESTPLAN_COMPLETED][] | Not Started | [${name.upper()} Testplan]({{<relref "dv/index.md#testplan" >}})

Eunchan Kim

2019-10-28 23:23:40 -0700

[diff] [blame]

134

Testbench | [TB_TOP_CREATED][] | Not Started |

135

Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started |

Pirmin Vogel

2020-03-13 12:12:15 +0100

[diff] [blame]

136

Testbench | [SIM_TB_ENV_CREATED][] | Not Started |

137

Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Not Started |

138

Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Not Started |

Eunchan Kim

2019-10-28 23:23:40 -0700

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139

Testbench | [TB_GEN_AUTOMATED][] | Not Started |

Cindy Chen

2020-11-11 10:28:54 -0800

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140

Tests | [SIM_SMOKE_TEST_PASSING][] | Not Started |

Pirmin Vogel

2020-03-13 12:12:15 +0100

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141

Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Not Started |

142

Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | Not Started |

143

Tool Setup | [SIM_ALT_TOOL_SETUP][] | Not Started |

Cindy Chen

2020-11-11 10:28:54 -0800

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144

Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Not Started |

Pirmin Vogel

2020-03-13 12:12:15 +0100

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145

Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Not Started |

146

Regression | [FPV_REGRESSION_SETUP][] | Not Started |

147

Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Not Started |

Cindy Chen

2020-11-04 10:32:54 -0800

[diff] [blame]

148

Code Quality | [TB_LINT_SETUP][] | Not Started |

Eunchan Kim

2019-10-28 23:23:40 -0700

[diff] [blame]

149

Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Not Started |

150

Review | [DESIGN_SPEC_REVIEWED][] | Not Started |

Srikrishna Iyer

2021-05-14 14:26:53 -0700

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151

Review | [TESTPLAN_REVIEWED][] | Not Started |

Pirmin Vogel

2020-03-13 12:12:15 +0100

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152

Review | [STD_TEST_CATEGORIES_PLANNED][] | Not Started | Exception (?)

Eunchan Kim

2019-10-28 23:23:40 -0700

[diff] [blame]

153

Review | [V2_CHECKLIST_SCOPED][] | Not Started |

Eunchan Kim

2019-10-28 23:23:40 -0700

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154

Michael Schaffner

b773efa

2020-12-11 15:11:55 -0800

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155

[DV_DOC_DRAFT_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_doc_draft_completed" >}}

Srikrishna Iyer

2021-05-14 14:26:53 -0700

[diff] [blame]

156

[TESTPLAN_COMPLETED]: {{<relref "/doc/project/checklist.md#testplan_completed" >}}

Michael Schaffner

2020-10-09 19:20:39 -0700

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157

[TB_TOP_CREATED]: {{<relref "/doc/project/checklist.md#tb_top_created" >}}

158

[PRELIMINARY_ASSERTION_CHECKS_ADDED]: {{<relref "/doc/project/checklist.md#preliminary_assertion_checks_added" >}}

159

[SIM_TB_ENV_CREATED]: {{<relref "/doc/project/checklist.md#sim_tb_env_created" >}}

160

[SIM_RAL_MODEL_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#sim_ral_model_gen_automated" >}}

161

[CSR_CHECK_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#csr_check_gen_automated" >}}

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[TB_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#tb_gen_automated" >}}

Cindy Chen

2020-11-11 10:28:54 -0800

[diff] [blame]

163

[SIM_SMOKE_TEST_PASSING]: {{<relref "/doc/project/checklist.md#sim_smoke_test_passing" >}}

Michael Schaffner

2020-10-09 19:20:39 -0700

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164

[SIM_CSR_MEM_TEST_SUITE_PASSING]: {{<relref "/doc/project/checklist.md#sim_csr_mem_test_suite_passing" >}}

165

[FPV_MAIN_ASSERTIONS_PROVEN]: {{<relref "/doc/project/checklist.md#fpv_main_assertions_proven" >}}

166

[SIM_ALT_TOOL_SETUP]: {{<relref "/doc/project/checklist.md#sim_alt_tool_setup" >}}

Cindy Chen

2020-11-11 10:28:54 -0800

[diff] [blame]

167

[SIM_SMOKE_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#sim_smoke_regression_setup" >}}

Michael Schaffner

2020-10-09 19:20:39 -0700

[diff] [blame]

168

[SIM_NIGHTLY_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#sim_nightly_regression_setup" >}}

169

[FPV_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#fpv_regression_setup" >}}

170

[SIM_COVERAGE_MODEL_ADDED]: {{<relref "/doc/project/checklist.md#sim_coverage_model_added" >}}

Cindy Chen

2020-11-04 10:32:54 -0800

[diff] [blame]

171

[TB_LINT_SETUP]: {{<relref "/doc/project/checklist.md#tb_lint_setup" >}}

Michael Schaffner

2020-10-09 19:20:39 -0700

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172

[PRE_VERIFIED_SUB_MODULES_V1]: {{<relref "/doc/project/checklist.md#pre_verified_sub_modules_v1" >}}

173

[DESIGN_SPEC_REVIEWED]: {{<relref "/doc/project/checklist.md#design_spec_reviewed" >}}

Srikrishna Iyer

2021-05-14 14:26:53 -0700

[diff] [blame]

174

[TESTPLAN_REVIEWED]: {{<relref "/doc/project/checklist.md#testplan_reviewed" >}}

Michael Schaffner

2020-10-09 19:20:39 -0700

[diff] [blame]

175

[STD_TEST_CATEGORIES_PLANNED]: {{<relref "/doc/project/checklist.md#std_test_categories_planned" >}}

176

[V2_CHECKLIST_SCOPED]: {{<relref "/doc/project/checklist.md#v2_checklist_scoped" >}}

Eunchan Kim

2019-10-28 23:23:40 -0700

[diff] [blame]

177

Philipp Wagner

2020-09-17 10:48:36 +0100

[diff] [blame]

178

<%text>### V2</%text>

Eunchan Kim

2019-10-28 23:23:40 -0700

[diff] [blame]

179

180

Type | Item | Resolution | Note/Collaterals

181

--------------|-----------------------------------------|-------------|------------------

Michael Schaffner

2020-10-09 19:20:39 -0700

[diff] [blame]

182

Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Not Started |

Srikrishna Iyer

2021-05-14 14:26:53 -0700

[diff] [blame]

183

Documentation | [DV_DOC_COMPLETED][] | Not Started |

184

Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Not Started |

Michael Schaffner

2020-10-09 19:20:39 -0700

[diff] [blame]

185

Testbench | [ALL_INTERFACES_EXERCISED][] | Not Started |

186

Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Not Started |

187

Testbench | [SIM_TB_ENV_COMPLETED][] | Not Started |

188

Tests | [SIM_ALL_TESTS_PASSING][] | Not Started |

189

Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | Not Started |

190

Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | Not Started |

191

Tests | [SIM_FW_SIMULATED][] | Not Started |

192

Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Not Started |

193

Coverage | [SIM_CODE_COVERAGE_V2][] | Not Started |

194

Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Not Started |

195

Coverage | [FPV_CODE_COVERAGE_V2][] | Not Started |

196

Coverage | [FPV_COI_COVERAGE_V2][] | Not Started |

Cindy Chen

2020-11-04 10:32:54 -0800

[diff] [blame]

197

Code Quality | [TB_LINT_PASS][] | Not Started |

Srikrishna Iyer

2021-05-14 14:26:53 -0700

[diff] [blame]

198

Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Not Started |

Michael Schaffner

2020-10-09 19:20:39 -0700

[diff] [blame]

199

Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Not Started |

200

Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Not Started |

Srikrishna Iyer

2021-05-14 14:26:53 -0700

[diff] [blame]

201

Review | [DV_DOC_TESTPLAN_REVIEWED][] | Not Started |

Michael Schaffner

2020-10-09 19:20:39 -0700

[diff] [blame]

202

Review | [V3_CHECKLIST_SCOPED][] | Not Started |

Eunchan Kim

2019-10-28 23:23:40 -0700

[diff] [blame]

203

Michael Schaffner

2020-10-09 19:20:39 -0700

[diff] [blame]

204

[DESIGN_DELTAS_CAPTURED_V2]: {{<relref "/doc/project/checklist.md#design_deltas_captured_v2" >}}

Srikrishna Iyer

2021-05-14 14:26:53 -0700

[diff] [blame]

205

[DV_DOC_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_doc_completed" >}}

206

[FUNCTIONAL_COVERAGE_IMPLEMENTED]: {{<relref "/doc/project/checklist.md#functional_coverage_implemented" >}}

Michael Schaffner

2020-10-09 19:20:39 -0700

[diff] [blame]

207

[ALL_INTERFACES_EXERCISED]: {{<relref "/doc/project/checklist.md#all_interfaces_exercised" >}}

208

[ALL_ASSERTION_CHECKS_ADDED]: {{<relref "/doc/project/checklist.md#all_assertion_checks_added" >}}

209

[SIM_TB_ENV_COMPLETED]: {{<relref "/doc/project/checklist.md#sim_tb_env_completed" >}}

210

[SIM_ALL_TESTS_PASSING]: {{<relref "/doc/project/checklist.md#sim_all_tests_passing" >}}

211

[FPV_ALL_ASSERTIONS_WRITTEN]: {{<relref "/doc/project/checklist.md#fpv_all_assertions_written" >}}

212

[FPV_ALL_ASSUMPTIONS_REVIEWED]: {{<relref "/doc/project/checklist.md#fpv_all_assumptions_reviewed" >}}

213

[SIM_FW_SIMULATED]: {{<relref "/doc/project/checklist.md#sim_fw_simulated" >}}

214

[SIM_NIGHTLY_REGRESSION_V2]: {{<relref "/doc/project/checklist.md#sim_nightly_regression_v2" >}}

215

[SIM_CODE_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#sim_code_coverage_v2" >}}

216

[SIM_FUNCTIONAL_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#sim_functional_coverage_v2" >}}

217

[FPV_CODE_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#fpv_code_coverage_v2" >}}

218

[FPV_COI_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#fpv_coi_coverage_v2" >}}

Cindy Chen

2020-11-04 10:32:54 -0800

[diff] [blame]

219

[TB_LINT_PASS]: {{<relref "/doc/project/checklist.md#tb_lint_pass" >}}

Srikrishna Iyer

2021-05-14 14:26:53 -0700

[diff] [blame]

220

[PRE_VERIFIED_SUB_MODULES_V2]: {{<relref "/doc/project/checklist.md#pre_verified_sub_modules_v2" >}}

Michael Schaffner

2020-10-09 19:20:39 -0700

[diff] [blame]

221

[NO_HIGH_PRIORITY_ISSUES_PENDING]: {{<relref "/doc/project/checklist.md#no_high_priority_issues_pending" >}}

222

[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:{{<relref "/doc/project/checklist.md#all_low_priority_issues_root_caused" >}}

Srikrishna Iyer

2021-05-14 14:26:53 -0700

[diff] [blame]

223

[DV_DOC_TESTPLAN_REVIEWED]: {{<relref "/doc/project/checklist.md#dv_doc_testplan_reviewed" >}}

Michael Schaffner

2020-10-09 19:20:39 -0700

[diff] [blame]

224

[V3_CHECKLIST_SCOPED]: {{<relref "/doc/project/checklist.md#v3_checklist_scoped" >}}

Eunchan Kim

2019-10-28 23:23:40 -0700

[diff] [blame]

225

Michael Schaffner

2021-11-04 15:58:58 -0700

[diff] [blame]

226

<%text>### V2S</%text>

227

228

Type | Item | Resolution | Note/Collaterals

229

--------------|-----------------------------------------|-------------|------------------

Weicai Yang

6a25a62

2022-02-02 11:54:22 -0800

[diff] [blame]

230

Tests | [FPV_SEC_CM_VERIFIED][] | Not Started |

231

Tests | [SIM_SEC_CM_VERIFIED][] | Not Started |

Michael Schaffner

2021-11-04 15:58:58 -0700

[diff] [blame]

232

Weicai Yang

6a25a62

2022-02-02 11:54:22 -0800

[diff] [blame]

233

[FPV_SEC_CM_VERIFIED]: {{<relref "/doc/project/checklist.md#fpv_sec_cm_verified" >}}

234

[SIM_SEC_CM_VERIFIED]: {{<relref "/doc/project/checklist.md#sim_sec_cm_verified" >}}

Michael Schaffner

2021-11-04 15:58:58 -0700

[diff] [blame]

235

Philipp Wagner

2020-09-17 10:48:36 +0100

[diff] [blame]

236

<%text>### V3</%text>

Eunchan Kim

2019-10-28 23:23:40 -0700

[diff] [blame]

237

238

Type | Item | Resolution | Note/Collaterals

239

--------------|-----------------------------------|-------------|------------------

Michael Schaffner

2020-10-09 19:20:39 -0700

[diff] [blame]

240

Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started |

Michael Schaffner

2020-10-09 19:20:39 -0700

[diff] [blame]

241

Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started |

242

Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started |

243

Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started |

244

Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started |

245

Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started |

246

Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started |

247

Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started |

Srikrishna Iyer

2021-05-14 14:26:53 -0700

[diff] [blame]

248

Code Quality | [ALL_TODOS_RESOLVED][] | Not Started |

Michael Schaffner

2020-10-09 19:20:39 -0700

[diff] [blame]

249

Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started |

Cindy Chen

2020-11-04 10:32:54 -0800

[diff] [blame]

250

Code Quality | [TB_LINT_COMPLETE][] | Not Started |

Michael Schaffner

2020-10-09 19:20:39 -0700

[diff] [blame]

251

Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started |

Srikrishna Iyer

2021-05-14 14:26:53 -0700

[diff] [blame]

252

Issues | [NO_ISSUES_PENDING][] | Not Started |

Michael Schaffner

2020-10-09 19:20:39 -0700

[diff] [blame]

253

Review | Reviewer(s) | Not Started |

254

Review | Signoff date | Not Started |

Eunchan Kim

2019-10-28 23:23:40 -0700

[diff] [blame]

255

Michael Schaffner

2020-10-09 19:20:39 -0700

[diff] [blame]

256

[DESIGN_DELTAS_CAPTURED_V3]: {{<relref "/doc/project/checklist.md#design_deltas_captured_v3" >}}

Michael Schaffner

2020-10-09 19:20:39 -0700

[diff] [blame]

257

[X_PROP_ANALYSIS_COMPLETED]: {{<relref "/doc/project/checklist.md#x_prop_analysis_completed" >}}

258

[FPV_ASSERTIONS_PROVEN_AT_V3]: {{<relref "/doc/project/checklist.md#fpv_assertions_proven_at_v3" >}}

259

[SIM_NIGHTLY_REGRESSION_AT_V3]: {{<relref "/doc/project/checklist.md#sim_nightly_regression_at_v3" >}}

260

[SIM_CODE_COVERAGE_AT_100]: {{<relref "/doc/project/checklist.md#sim_code_coverage_at_100" >}}

261

[SIM_FUNCTIONAL_COVERAGE_AT_100]:{{<relref "/doc/project/checklist.md#sim_functional_coverage_at_100" >}}

262

[FPV_CODE_COVERAGE_AT_100]: {{<relref "/doc/project/checklist.md#fpv_code_coverage_at_100" >}}

263

[FPV_COI_COVERAGE_AT_100]: {{<relref "/doc/project/checklist.md#fpv_coi_coverage_at_100" >}}

Srikrishna Iyer

2021-05-14 14:26:53 -0700

[diff] [blame]

264

[ALL_TODOS_RESOLVED]: {{<relref "/doc/project/checklist.md#all_todos_resolved" >}}

Michael Schaffner

2020-10-09 19:20:39 -0700

[diff] [blame]

265

[NO_TOOL_WARNINGS_THROWN]: {{<relref "/doc/project/checklist.md#no_tool_warnings_thrown" >}}

Cindy Chen

2020-11-04 10:32:54 -0800

[diff] [blame]

266

[TB_LINT_COMPLETE]: {{<relref "/doc/project/checklist.md#tb_lint_complete" >}}

Michael Schaffner

2020-10-09 19:20:39 -0700

[diff] [blame]

267

[PRE_VERIFIED_SUB_MODULES_V3]: {{<relref "/doc/project/checklist.md#pre_verified_sub_modules_v3" >}}

Srikrishna Iyer