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Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -04001// Copyright lowRISC contributors.
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4
Miguel Young de la Sotafdce22f2020-07-06 12:33:10 -04005#include "sw/device/lib/dif/dif_i2c.h"
6
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -04007#include <cstring>
8#include <limits>
9#include <ostream>
10
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -040011#include "gtest/gtest.h"
12#include "sw/device/lib/base/mmio.h"
Drew Macraef9f2e5f2022-06-22 15:57:07 -040013#include "sw/device/lib/base/mock_mmio.h"
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -050014#include "sw/device/lib/dif/dif_test_base.h"
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -040015
Miguel Young de la Sotafdce22f2020-07-06 12:33:10 -040016#include "i2c_regs.h" // Generated.
17
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -040018// We define global namespace == and << to make `dif_i2c_timing_params_t` work
19// nicely with EXPECT_EQ.
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -040020bool operator==(dif_i2c_config_t a, dif_i2c_config_t b) {
Miguel Young de la Sota60355c12020-09-29 15:05:56 -040021 // We just do a dumb memcmp. The config params struct is essentially an array
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -040022 // of half-words, so we won't run into padding issues.
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -040023 return std::memcmp(&a, &b, sizeof(dif_i2c_config_t)) == 0;
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -040024}
25
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -040026std::ostream &operator<<(std::ostream &os, const dif_i2c_config_t &params) {
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -040027 return os << "{\n"
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -040028 << " .scl_time_high_cycles = " << params.scl_time_high_cycles
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -040029 << ",\n"
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -040030 << " .scl_time_low_cycles = " << params.scl_time_low_cycles
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -040031 << ",\n"
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -040032 << " .rise_cycles = " << params.rise_cycles << ",\n"
33 << " .fall_cycles = " << params.fall_cycles << ",\n"
34 << " .start_signal_setup_cycles = "
35 << params.start_signal_setup_cycles << ",\n"
36 << " .start_signal_hold_cycles = "
37 << params.start_signal_hold_cycles << ",\n"
38 << " .data_signal_setup_cycles = "
39 << params.data_signal_setup_cycles << ",\n"
40 << " .data_signal_hold_cycles = " << params.data_signal_hold_cycles
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -040041 << ",\n"
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -040042 << " .stop_signal_setup_cycles = "
43 << params.stop_signal_setup_cycles << ",\n"
44 << " .stop_signal_hold_cycles = " << params.stop_signal_hold_cycles
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -040045 << ",\n"
46 << "}";
47}
48
Drew Macrae8bf80122022-09-16 10:46:50 -040049// We define global namespace == and << to make `dif_i2c_status_t` work
50// nicely with EXPECT_EQ.
51bool operator==(dif_i2c_status_t a, dif_i2c_status_t b) {
52 return a.enable_host == b.enable_host && a.enable_target == b.enable_target &&
53 a.line_loopback == b.line_loopback &&
54 a.fmt_fifo_full == b.fmt_fifo_full &&
55 a.rx_fifo_full == b.rx_fifo_full &&
56 a.fmt_fifo_empty == b.fmt_fifo_empty &&
57 a.rx_fifo_empty == b.rx_fifo_empty && a.host_idle == b.host_idle &&
58 a.target_idle == b.target_idle && a.tx_fifo_full == b.tx_fifo_full &&
59 a.acq_fifo_full == b.acq_fifo_full &&
60 a.tx_fifo_empty == b.tx_fifo_empty &&
61 a.acq_fifo_empty == b.acq_fifo_empty;
62}
63
64std::ostream &operator<<(std::ostream &os, const dif_i2c_status_t &params) {
65 return os << "{\n"
66 << " .enable_host = " << params.enable_host << ",\n"
67 << " .enable_target = " << params.enable_target << ",\n"
68 << " .line_loopback = " << params.line_loopback << ",\n"
69 << " .fmt_fifo_full = " << params.fmt_fifo_full << ",\n"
70 << " .rx_fifo_full = " << params.rx_fifo_full << ",\n"
71 << " .fmt_fifo_empty = " << params.fmt_fifo_empty << ",\n"
72 << " .rx_fifo_empty = " << params.rx_fifo_empty << ",\n"
73 << " .host_idle = " << params.host_idle << ",\n"
74 << " .target_idle = " << params.target_idle << ",\n"
75 << " .tx_fifo_full = " << params.tx_fifo_full << ",\n"
76 << " .acq_fifo_full = " << params.acq_fifo_full << ",\n"
77 << " .tx_fifo_empty = " << params.tx_fifo_empty << ",\n"
78 << " .acq_fifo_empty = " << params.acq_fifo_empty << ",\n"
79 << "}";
80}
81
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -040082namespace dif_i2c_unittest {
83namespace {
84using ::mock_mmio::LeInt;
85using ::mock_mmio::MmioTest;
86using ::mock_mmio::MockDevice;
87
Timothy Trippel5899a1d2021-09-24 01:36:13 +000088class I2cTest : public testing::Test, public MmioTest {
89 protected:
90 dif_i2c_t i2c_ = {.base_addr = dev().region()};
91};
92
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -040093// "Base" configs consisting of harware timings, in "slow" and "fast" variants.
94constexpr dif_i2c_timing_config_t kBaseConfigSlow = {
95 .lowest_target_device_speed =
96 kDifI2cSpeedStandard, // Remove once we upgrade the host compiler.
97 .clock_period_nanos = 90,
98 .sda_rise_nanos = 250,
99 .sda_fall_nanos = 220,
100};
101
102constexpr dif_i2c_timing_config_t kBaseConfigFast = {
103 .lowest_target_device_speed =
104 kDifI2cSpeedStandard, // Remove once we upgrade the host compiler.
105 .clock_period_nanos = 20,
106 .sda_rise_nanos = 120,
107 .sda_fall_nanos = 130,
108};
109
110TEST(ComputeTimingTest, StandardSpeed) {
111 dif_i2c_timing_config_t config;
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400112 dif_i2c_config_t params, expected;
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400113
114 config = kBaseConfigSlow;
115 config.lowest_target_device_speed = kDifI2cSpeedStandard;
116 expected = {
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400117 .scl_time_high_cycles = 53,
118 .scl_time_low_cycles = 53,
119 .rise_cycles = 3,
120 .fall_cycles = 3,
121 .start_signal_setup_cycles = 53,
122 .start_signal_hold_cycles = 45,
123 .data_signal_setup_cycles = 3,
Timothy Chene53d5662022-09-06 16:42:33 -0700124 .data_signal_hold_cycles = 1,
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400125 .stop_signal_setup_cycles = 45,
126 .stop_signal_hold_cycles = 53,
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400127 };
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500128 EXPECT_DIF_OK(dif_i2c_compute_timing(config, &params));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400129 EXPECT_EQ(params, expected);
130
131 config = kBaseConfigFast;
132 config.lowest_target_device_speed = kDifI2cSpeedStandard;
133 expected = {
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400134 .scl_time_high_cycles = 252,
135 .scl_time_low_cycles = 235,
136 .rise_cycles = 6,
137 .fall_cycles = 7,
138 .start_signal_setup_cycles = 235,
139 .start_signal_hold_cycles = 200,
140 .data_signal_setup_cycles = 13,
Timothy Chene53d5662022-09-06 16:42:33 -0700141 .data_signal_hold_cycles = 1,
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400142 .stop_signal_setup_cycles = 200,
143 .stop_signal_hold_cycles = 235,
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400144 };
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500145 EXPECT_DIF_OK(dif_i2c_compute_timing(config, &params));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400146 EXPECT_EQ(params, expected);
147
148 config = kBaseConfigSlow;
149 config.lowest_target_device_speed = kDifI2cSpeedStandard;
150 config.scl_period_nanos = 11000;
151 expected = {
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400152 .scl_time_high_cycles = 64,
153 .scl_time_low_cycles = 53,
154 .rise_cycles = 3,
155 .fall_cycles = 3,
156 .start_signal_setup_cycles = 53,
157 .start_signal_hold_cycles = 45,
158 .data_signal_setup_cycles = 3,
Timothy Chene53d5662022-09-06 16:42:33 -0700159 .data_signal_hold_cycles = 1,
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400160 .stop_signal_setup_cycles = 45,
161 .stop_signal_hold_cycles = 53,
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400162 };
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500163 EXPECT_DIF_OK(dif_i2c_compute_timing(config, &params));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400164 EXPECT_EQ(params, expected);
165}
166
167TEST(ComputeTimingTest, FastSpeed) {
168 dif_i2c_timing_config_t config;
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400169 dif_i2c_config_t params, expected;
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400170
171 config = kBaseConfigSlow;
172 config.lowest_target_device_speed = kDifI2cSpeedFast;
173 expected = {
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400174 .scl_time_high_cycles = 7,
175 .scl_time_low_cycles = 15,
176 .rise_cycles = 3,
177 .fall_cycles = 3,
178 .start_signal_setup_cycles = 7,
179 .start_signal_hold_cycles = 7,
180 .data_signal_setup_cycles = 2,
Timothy Chene53d5662022-09-06 16:42:33 -0700181 .data_signal_hold_cycles = 1,
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400182 .stop_signal_setup_cycles = 7,
183 .stop_signal_hold_cycles = 15,
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400184 };
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500185 EXPECT_DIF_OK(dif_i2c_compute_timing(config, &params));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400186 EXPECT_EQ(params, expected);
187
188 config = kBaseConfigFast;
189 config.lowest_target_device_speed = kDifI2cSpeedFast;
190 expected = {
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400191 .scl_time_high_cycles = 47,
192 .scl_time_low_cycles = 65,
193 .rise_cycles = 6,
194 .fall_cycles = 7,
195 .start_signal_setup_cycles = 30,
196 .start_signal_hold_cycles = 30,
197 .data_signal_setup_cycles = 5,
Timothy Chene53d5662022-09-06 16:42:33 -0700198 .data_signal_hold_cycles = 1,
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400199 .stop_signal_setup_cycles = 30,
200 .stop_signal_hold_cycles = 65,
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400201 };
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500202 EXPECT_DIF_OK(dif_i2c_compute_timing(config, &params));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400203 EXPECT_EQ(params, expected);
204
205 config = kBaseConfigSlow;
206 config.lowest_target_device_speed = kDifI2cSpeedFast;
207 config.scl_period_nanos = 8000;
208 expected = {
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400209 .scl_time_high_cycles = 68,
210 .scl_time_low_cycles = 15,
211 .rise_cycles = 3,
212 .fall_cycles = 3,
213 .start_signal_setup_cycles = 7,
214 .start_signal_hold_cycles = 7,
215 .data_signal_setup_cycles = 2,
Timothy Chene53d5662022-09-06 16:42:33 -0700216 .data_signal_hold_cycles = 1,
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400217 .stop_signal_setup_cycles = 7,
218 .stop_signal_hold_cycles = 15,
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400219 };
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500220 EXPECT_DIF_OK(dif_i2c_compute_timing(config, &params));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400221 EXPECT_EQ(params, expected);
222}
223
224TEST(ComputeTimingTest, FastPlusSpeed) {
225 dif_i2c_timing_config_t config;
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400226 dif_i2c_config_t params, expected;
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400227
228 config = kBaseConfigFast;
229 config.lowest_target_device_speed = kDifI2cSpeedFastPlus;
230 expected = {
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400231 .scl_time_high_cycles = 13,
232 .scl_time_low_cycles = 25,
233 .rise_cycles = 6,
234 .fall_cycles = 7,
235 .start_signal_setup_cycles = 13,
236 .start_signal_hold_cycles = 13,
237 .data_signal_setup_cycles = 3,
Timothy Chene53d5662022-09-06 16:42:33 -0700238 .data_signal_hold_cycles = 1,
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400239 .stop_signal_setup_cycles = 13,
240 .stop_signal_hold_cycles = 25,
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400241 };
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500242 EXPECT_DIF_OK(dif_i2c_compute_timing(config, &params));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400243 EXPECT_EQ(params, expected);
244
245 config = kBaseConfigFast;
246 config.lowest_target_device_speed = kDifI2cSpeedFastPlus;
247 config.scl_period_nanos = 1500;
248 expected = {
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400249 .scl_time_high_cycles = 37,
250 .scl_time_low_cycles = 25,
251 .rise_cycles = 6,
252 .fall_cycles = 7,
253 .start_signal_setup_cycles = 13,
254 .start_signal_hold_cycles = 13,
255 .data_signal_setup_cycles = 3,
Timothy Chene53d5662022-09-06 16:42:33 -0700256 .data_signal_hold_cycles = 1,
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400257 .stop_signal_setup_cycles = 13,
258 .stop_signal_hold_cycles = 25,
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400259 };
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500260 EXPECT_DIF_OK(dif_i2c_compute_timing(config, &params));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400261 EXPECT_EQ(params, expected);
262}
263
264TEST(ComputeTimingTest, NullArgs) {
Miguel Young de la Sotaf0896512022-03-10 14:17:42 -0500265 EXPECT_DIF_BADARG(dif_i2c_compute_timing(kBaseConfigFast, nullptr));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400266}
267
Miguel Young de la Sota60355c12020-09-29 15:05:56 -0400268class ConfigTest : public I2cTest {};
269
270TEST_F(ConfigTest, NormalInit) {
271 dif_i2c_config_t config = {
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400272 .scl_time_high_cycles = 252,
273 .scl_time_low_cycles = 235,
274 .rise_cycles = 6,
275 .fall_cycles = 7,
276 .start_signal_setup_cycles = 235,
277 .start_signal_hold_cycles = 200,
278 .data_signal_setup_cycles = 13,
Timothy Chene53d5662022-09-06 16:42:33 -0700279 .data_signal_hold_cycles = 1,
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400280 .stop_signal_setup_cycles = 200,
281 .stop_signal_hold_cycles = 235,
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400282 };
283
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400284 EXPECT_WRITE32(I2C_TIMING0_REG_OFFSET,
285 {
Miguel Young de la Sota60355c12020-09-29 15:05:56 -0400286 {I2C_TIMING0_THIGH_OFFSET, config.scl_time_high_cycles},
287 {I2C_TIMING0_TLOW_OFFSET, config.scl_time_low_cycles},
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400288 });
289 EXPECT_WRITE32(I2C_TIMING1_REG_OFFSET,
290 {
Miguel Young de la Sota60355c12020-09-29 15:05:56 -0400291 {I2C_TIMING1_T_R_OFFSET, config.rise_cycles},
292 {I2C_TIMING1_T_F_OFFSET, config.fall_cycles},
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400293 });
294 EXPECT_WRITE32(
295 I2C_TIMING2_REG_OFFSET,
296 {
Miguel Young de la Sota60355c12020-09-29 15:05:56 -0400297 {I2C_TIMING2_TSU_STA_OFFSET, config.start_signal_setup_cycles},
298 {I2C_TIMING2_THD_STA_OFFSET, config.start_signal_hold_cycles},
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400299 });
300 EXPECT_WRITE32(
301 I2C_TIMING3_REG_OFFSET,
302 {
Miguel Young de la Sota60355c12020-09-29 15:05:56 -0400303 {I2C_TIMING3_TSU_DAT_OFFSET, config.data_signal_setup_cycles},
304 {I2C_TIMING3_THD_DAT_OFFSET, config.data_signal_hold_cycles},
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400305 });
306 EXPECT_WRITE32(
307 I2C_TIMING4_REG_OFFSET,
308 {
Miguel Young de la Sota60355c12020-09-29 15:05:56 -0400309 {I2C_TIMING4_TSU_STO_OFFSET, config.stop_signal_setup_cycles},
310 {I2C_TIMING4_T_BUF_OFFSET, config.stop_signal_hold_cycles},
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400311 });
312
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500313 EXPECT_DIF_OK(dif_i2c_configure(&i2c_, config));
Drew Macrae8bf80122022-09-16 10:46:50 -0400314
315 dif_i2c_status status, expectedStatus;
316 EXPECT_READ32(I2C_CTRL_REG_OFFSET, 0x00000003); // Host and Target active
317 EXPECT_READ32(I2C_STATUS_REG_OFFSET, 0x0000033c); // All empty and idle
318 EXPECT_DIF_OK(dif_i2c_get_status(&i2c_, &status));
319 expectedStatus = {
320 .enable_host = true,
321 .enable_target = true,
322 .fmt_fifo_empty = true,
323 .rx_fifo_empty = true,
324 .host_idle = true,
325 .target_idle = true,
326 .tx_fifo_empty = true,
327 .acq_fifo_empty = true,
328 };
329 EXPECT_EQ(status, expectedStatus);
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400330}
331
Miguel Young de la Sota2e8bd9a2020-09-29 14:44:26 -0400332TEST_F(ConfigTest, NullArgs) {
Drew Macrae8bf80122022-09-16 10:46:50 -0400333 dif_i2c_status status;
334 EXPECT_DIF_BADARG(dif_i2c_get_status(nullptr, &status));
335 EXPECT_DIF_BADARG(dif_i2c_get_status(&i2c_, nullptr));
Miguel Young de la Sotaf0896512022-03-10 14:17:42 -0500336 EXPECT_DIF_BADARG(dif_i2c_configure(nullptr, {}));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400337}
338
339class FifoCtrlTest : public I2cTest {};
340
341TEST_F(FifoCtrlTest, RxReset) {
Miguel Young de la Sota4e1a4a32020-11-05 10:08:52 -0500342 EXPECT_MASK32(I2C_FIFO_CTRL_REG_OFFSET,
343 {{I2C_FIFO_CTRL_RXRST_BIT, 0x1, 0x1}});
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500344 EXPECT_DIF_OK(dif_i2c_reset_rx_fifo(&i2c_));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400345}
346
347TEST_F(FifoCtrlTest, RxNullArgs) {
Miguel Young de la Sotaf0896512022-03-10 14:17:42 -0500348 EXPECT_DIF_BADARG(dif_i2c_reset_rx_fifo(nullptr));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400349}
350
351TEST_F(FifoCtrlTest, FmtReset) {
Miguel Young de la Sota4e1a4a32020-11-05 10:08:52 -0500352 EXPECT_MASK32(I2C_FIFO_CTRL_REG_OFFSET,
353 {{I2C_FIFO_CTRL_FMTRST_BIT, 0x1, 0x1}});
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500354 EXPECT_DIF_OK(dif_i2c_reset_fmt_fifo(&i2c_));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400355}
356
357TEST_F(FifoCtrlTest, FmtNullArgs) {
Miguel Young de la Sotaf0896512022-03-10 14:17:42 -0500358 EXPECT_DIF_BADARG(dif_i2c_reset_fmt_fifo(nullptr));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400359}
360
Drew Macrae8bf80122022-09-16 10:46:50 -0400361TEST_F(FifoCtrlTest, AcqReset) {
362 EXPECT_MASK32(I2C_FIFO_CTRL_REG_OFFSET,
363 {{I2C_FIFO_CTRL_ACQRST_BIT, 0x1, 0x1}});
364 EXPECT_DIF_OK(dif_i2c_reset_acq_fifo(&i2c_));
365}
366
367TEST_F(FifoCtrlTest, AcqNullArgs) {
368 EXPECT_DIF_BADARG(dif_i2c_reset_acq_fifo(nullptr));
369}
370
371TEST_F(FifoCtrlTest, TxReset) {
372 EXPECT_MASK32(I2C_FIFO_CTRL_REG_OFFSET,
373 {{I2C_FIFO_CTRL_TXRST_BIT, 0x1, 0x1}});
374 EXPECT_DIF_OK(dif_i2c_reset_tx_fifo(&i2c_));
375}
376
377TEST_F(FifoCtrlTest, TxNullArgs) {
378 EXPECT_DIF_BADARG(dif_i2c_reset_tx_fifo(nullptr));
379}
380
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400381TEST_F(FifoCtrlTest, SetLevels) {
Sam Elliottae1bab62020-10-15 16:43:05 +0100382 EXPECT_MASK32(I2C_FIFO_CTRL_REG_OFFSET,
383 {
384 {
385 I2C_FIFO_CTRL_RXILVL_OFFSET,
386 I2C_FIFO_CTRL_RXILVL_MASK,
387 I2C_FIFO_CTRL_RXILVL_VALUE_RXLVL1,
388 },
389 {
390 I2C_FIFO_CTRL_FMTILVL_OFFSET,
391 I2C_FIFO_CTRL_FMTILVL_MASK,
392 I2C_FIFO_CTRL_FMTILVL_VALUE_FMTLVL1,
393 },
394 });
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500395 EXPECT_DIF_OK(
396 dif_i2c_set_watermarks(&i2c_, kDifI2cLevel1Byte, kDifI2cLevel1Byte));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400397
Sam Elliottae1bab62020-10-15 16:43:05 +0100398 EXPECT_MASK32(I2C_FIFO_CTRL_REG_OFFSET,
399 {
400 {
401 I2C_FIFO_CTRL_RXILVL_OFFSET,
402 I2C_FIFO_CTRL_RXILVL_MASK,
403 I2C_FIFO_CTRL_RXILVL_VALUE_RXLVL4,
404 },
405 {
406 I2C_FIFO_CTRL_FMTILVL_OFFSET,
407 I2C_FIFO_CTRL_FMTILVL_MASK,
408 I2C_FIFO_CTRL_FMTILVL_VALUE_FMTLVL16,
409 },
410 });
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500411 EXPECT_DIF_OK(
412 dif_i2c_set_watermarks(&i2c_, kDifI2cLevel4Byte, kDifI2cLevel16Byte));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400413
Sam Elliottae1bab62020-10-15 16:43:05 +0100414 EXPECT_MASK32(I2C_FIFO_CTRL_REG_OFFSET,
415 {
416 {
417 I2C_FIFO_CTRL_RXILVL_OFFSET,
418 I2C_FIFO_CTRL_RXILVL_MASK,
419 I2C_FIFO_CTRL_RXILVL_VALUE_RXLVL30,
420 },
421 {
422 I2C_FIFO_CTRL_FMTILVL_OFFSET,
423 I2C_FIFO_CTRL_FMTILVL_MASK,
424 I2C_FIFO_CTRL_FMTILVL_VALUE_FMTLVL8,
425 },
426 });
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500427 EXPECT_DIF_OK(
428 dif_i2c_set_watermarks(&i2c_, kDifI2cLevel30Byte, kDifI2cLevel8Byte));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400429
Miguel Young de la Sotaf0896512022-03-10 14:17:42 -0500430 EXPECT_DIF_BADARG(
431 dif_i2c_set_watermarks(&i2c_, kDifI2cLevel30Byte, kDifI2cLevel30Byte));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400432}
433
434TEST_F(FifoCtrlTest, SetLevelsNullArgs) {
Miguel Young de la Sotaf0896512022-03-10 14:17:42 -0500435 EXPECT_DIF_BADARG(
436 dif_i2c_set_watermarks(nullptr, kDifI2cLevel4Byte, kDifI2cLevel16Byte));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400437}
438
439class ControlTest : public I2cTest {};
440
441TEST_F(ControlTest, HostEnable) {
Miguel Young de la Sota4e1a4a32020-11-05 10:08:52 -0500442 EXPECT_MASK32(I2C_CTRL_REG_OFFSET, {{I2C_CTRL_ENABLEHOST_BIT, 0x1, 0x1}});
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500443 EXPECT_DIF_OK(dif_i2c_host_set_enabled(&i2c_, kDifToggleEnabled));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400444
Miguel Young de la Sota4e1a4a32020-11-05 10:08:52 -0500445 EXPECT_MASK32(I2C_CTRL_REG_OFFSET, {{I2C_CTRL_ENABLEHOST_BIT, 0x1, 0x0}});
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500446 EXPECT_DIF_OK(dif_i2c_host_set_enabled(&i2c_, kDifToggleDisabled));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400447}
448
449TEST_F(ControlTest, HostEnableNullArgs) {
Miguel Young de la Sotaf0896512022-03-10 14:17:42 -0500450 EXPECT_DIF_BADARG(dif_i2c_host_set_enabled(nullptr, kDifToggleEnabled));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400451}
452
Drew Macrae8bf80122022-09-16 10:46:50 -0400453TEST_F(ControlTest, DeviceEnable) {
454 EXPECT_MASK32(I2C_CTRL_REG_OFFSET, {{I2C_CTRL_ENABLETARGET_BIT, 0x1, 0x1}});
455 EXPECT_DIF_OK(dif_i2c_device_set_enabled(&i2c_, kDifToggleEnabled));
456
457 EXPECT_MASK32(I2C_CTRL_REG_OFFSET, {{I2C_CTRL_ENABLETARGET_BIT, 0x1, 0x0}});
458 EXPECT_DIF_OK(dif_i2c_device_set_enabled(&i2c_, kDifToggleDisabled));
459}
460
461TEST_F(ControlTest, DeviceEnableNullArgs) {
462 EXPECT_DIF_BADARG(dif_i2c_device_set_enabled(nullptr, kDifToggleEnabled));
463}
464
465TEST_F(ControlTest, LLPBK) {
466 EXPECT_MASK32(I2C_CTRL_REG_OFFSET, {{I2C_CTRL_LLPBK_BIT, 0x1, 0x1}});
467 EXPECT_DIF_OK(dif_i2c_line_loopback_set_enabled(&i2c_, kDifToggleEnabled));
468
469 EXPECT_MASK32(I2C_CTRL_REG_OFFSET, {{I2C_CTRL_LLPBK_BIT, 0x1, 0x0}});
470 EXPECT_DIF_OK(dif_i2c_line_loopback_set_enabled(&i2c_, kDifToggleDisabled));
471}
472
473TEST_F(ControlTest, LLPBKNullArgs) {
474 EXPECT_DIF_BADARG(
475 dif_i2c_line_loopback_set_enabled(nullptr, kDifToggleEnabled));
476}
477
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400478class OverrideTest : public I2cTest {};
479
480TEST_F(OverrideTest, Enable) {
Miguel Young de la Sota4e1a4a32020-11-05 10:08:52 -0500481 EXPECT_MASK32(I2C_OVRD_REG_OFFSET, {{I2C_OVRD_TXOVRDEN_BIT, 0x1, 0x1}});
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500482 EXPECT_DIF_OK(dif_i2c_override_set_enabled(&i2c_, kDifToggleEnabled));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400483
Miguel Young de la Sota4e1a4a32020-11-05 10:08:52 -0500484 EXPECT_MASK32(I2C_OVRD_REG_OFFSET, {{I2C_OVRD_TXOVRDEN_BIT, 0x1, 0x0}});
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500485 EXPECT_DIF_OK(dif_i2c_override_set_enabled(&i2c_, kDifToggleDisabled));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400486}
487
488TEST_F(OverrideTest, EnableNullArgs) {
Miguel Young de la Sotaf0896512022-03-10 14:17:42 -0500489 EXPECT_DIF_BADARG(dif_i2c_override_set_enabled(nullptr, kDifToggleEnabled));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400490}
491
492TEST_F(OverrideTest, Drive) {
Miguel Young de la Sota4e1a4a32020-11-05 10:08:52 -0500493 EXPECT_MASK32(I2C_OVRD_REG_OFFSET, {
494 {I2C_OVRD_SCLVAL_BIT, 0x1, 0x0},
495 {I2C_OVRD_SDAVAL_BIT, 0x1, 0x0},
496 });
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500497 EXPECT_DIF_OK(dif_i2c_override_drive_pins(&i2c_, false, false));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400498
Miguel Young de la Sota4e1a4a32020-11-05 10:08:52 -0500499 EXPECT_MASK32(I2C_OVRD_REG_OFFSET, {
500 {I2C_OVRD_SCLVAL_BIT, 0x1, 0x0},
501 {I2C_OVRD_SDAVAL_BIT, 0x1, 0x1},
502 });
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500503 EXPECT_DIF_OK(dif_i2c_override_drive_pins(&i2c_, false, true));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400504
Miguel Young de la Sota4e1a4a32020-11-05 10:08:52 -0500505 EXPECT_MASK32(I2C_OVRD_REG_OFFSET, {
506 {I2C_OVRD_SCLVAL_BIT, 0x1, 0x1},
507 {I2C_OVRD_SDAVAL_BIT, 0x1, 0x1},
508 });
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500509 EXPECT_DIF_OK(dif_i2c_override_drive_pins(&i2c_, true, true));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400510}
511
512TEST_F(OverrideTest, DriveNullArgs) {
Miguel Young de la Sotaf0896512022-03-10 14:17:42 -0500513 EXPECT_DIF_BADARG(dif_i2c_override_drive_pins(nullptr, false, false));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400514}
515
516TEST_F(OverrideTest, Sample) {
517 uint16_t scl, sda;
518 EXPECT_READ32(I2C_VAL_REG_OFFSET, 0x10293847);
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500519 EXPECT_DIF_OK(dif_i2c_override_sample_pins(&i2c_, &scl, &sda));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400520 EXPECT_EQ(scl, 0x3847);
521 EXPECT_EQ(sda, 0x1029);
522
523 scl = 0, sda = 0;
524 EXPECT_READ32(I2C_VAL_REG_OFFSET, 0x10293847);
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500525 EXPECT_DIF_OK(dif_i2c_override_sample_pins(&i2c_, nullptr, &sda));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400526 EXPECT_EQ(scl, 0x0);
527 EXPECT_EQ(sda, 0x1029);
528
529 scl = 0, sda = 0;
530 EXPECT_READ32(I2C_VAL_REG_OFFSET, 0x10293847);
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500531 EXPECT_DIF_OK(dif_i2c_override_sample_pins(&i2c_, &scl, nullptr));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400532 EXPECT_EQ(scl, 0x3847);
533 EXPECT_EQ(sda, 0x0);
534}
535
536TEST_F(OverrideTest, SampleNullArgs) {
537 uint16_t scl, sda;
Miguel Young de la Sotaf0896512022-03-10 14:17:42 -0500538 EXPECT_DIF_BADARG(dif_i2c_override_sample_pins(nullptr, &scl, &sda));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400539}
540
541class FifoTest : public I2cTest {};
542
543TEST_F(FifoTest, GetLevels) {
Drew Macrae8bf80122022-09-16 10:46:50 -0400544 uint8_t rx, fmt, tx, acq;
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400545 EXPECT_READ32(I2C_FIFO_STATUS_REG_OFFSET, 0x10293847);
Drew Macrae8bf80122022-09-16 10:46:50 -0400546 EXPECT_DIF_OK(dif_i2c_get_fifo_levels(&i2c_, &fmt, &rx, &tx, &acq));
547 EXPECT_EQ(fmt, 0x47);
548 EXPECT_EQ(rx, 0x29);
549 EXPECT_EQ(tx, 0x38);
550 EXPECT_EQ(acq, 0x10);
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400551
Drew Macrae8bf80122022-09-16 10:46:50 -0400552 rx = 0, fmt = 0, tx = 0, acq = 0;
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400553 EXPECT_READ32(I2C_FIFO_STATUS_REG_OFFSET, 0x10293847);
Drew Macrae8bf80122022-09-16 10:46:50 -0400554 EXPECT_DIF_OK(dif_i2c_get_fifo_levels(&i2c_, &fmt, &rx, nullptr, nullptr));
555 EXPECT_EQ(fmt, 0x47);
556 EXPECT_EQ(rx, 0x29);
557 EXPECT_EQ(tx, 0x0);
558 EXPECT_EQ(acq, 0x0);
559
560 rx = 0, fmt = 0, tx = 0, acq = 0;
561 EXPECT_READ32(I2C_FIFO_STATUS_REG_OFFSET, 0x10293847);
562 EXPECT_DIF_OK(
563 dif_i2c_get_fifo_levels(&i2c_, &fmt, nullptr, nullptr, nullptr));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400564 EXPECT_EQ(rx, 0x0);
Drew Macrae8bf80122022-09-16 10:46:50 -0400565 EXPECT_EQ(fmt, 0x47);
566 EXPECT_EQ(tx, 0x0);
567 EXPECT_EQ(acq, 0x0);
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400568
Drew Macrae8bf80122022-09-16 10:46:50 -0400569 rx = 0, fmt = 0, tx = 0, acq = 0;
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400570 EXPECT_READ32(I2C_FIFO_STATUS_REG_OFFSET, 0x10293847);
Drew Macrae8bf80122022-09-16 10:46:50 -0400571 EXPECT_DIF_OK(dif_i2c_get_fifo_levels(&i2c_, nullptr, &rx, nullptr, nullptr));
572 EXPECT_EQ(rx, 0x29);
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400573 EXPECT_EQ(fmt, 0x0);
Drew Macrae8bf80122022-09-16 10:46:50 -0400574 EXPECT_EQ(tx, 0x0);
575 EXPECT_EQ(acq, 0x0);
576
577 rx = 0, fmt = 0, tx = 0, acq = 0;
578 EXPECT_READ32(I2C_FIFO_STATUS_REG_OFFSET, 0x10293847);
579 EXPECT_DIF_OK(dif_i2c_get_fifo_levels(&i2c_, nullptr, nullptr, &tx, &acq));
580 EXPECT_EQ(fmt, 0x0);
581 EXPECT_EQ(rx, 0x0);
582 EXPECT_EQ(tx, 0x38);
583 EXPECT_EQ(acq, 0x10);
584
585 rx = 0, fmt = 0, tx = 0, acq = 0;
586 EXPECT_READ32(I2C_FIFO_STATUS_REG_OFFSET, 0x10293847);
587 EXPECT_DIF_OK(dif_i2c_get_fifo_levels(&i2c_, nullptr, nullptr, &tx, nullptr));
588 EXPECT_EQ(rx, 0x0);
589 EXPECT_EQ(fmt, 0x0);
590 EXPECT_EQ(tx, 0x38);
591 EXPECT_EQ(acq, 0x0);
592
593 rx = 0, fmt = 0, tx = 0, acq = 0;
594 EXPECT_READ32(I2C_FIFO_STATUS_REG_OFFSET, 0x10293847);
595 EXPECT_DIF_OK(
596 dif_i2c_get_fifo_levels(&i2c_, nullptr, nullptr, nullptr, &acq));
597 EXPECT_EQ(rx, 0x0);
598 EXPECT_EQ(fmt, 0x0);
599 EXPECT_EQ(tx, 0x0);
600 EXPECT_EQ(acq, 0x10);
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400601}
602
603TEST_F(FifoTest, GetLevelsNullArgs) {
604 uint8_t rx, fmt;
Drew Macrae8bf80122022-09-16 10:46:50 -0400605 EXPECT_DIF_BADARG(
606 dif_i2c_get_fifo_levels(nullptr, &rx, &fmt, nullptr, nullptr));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400607}
608
609TEST_F(FifoTest, Read) {
610 uint8_t val;
611
612 EXPECT_READ32(I2C_RDATA_REG_OFFSET, 0xab);
613 EXPECT_READ32(I2C_RDATA_REG_OFFSET, 0xcd);
614 EXPECT_READ32(I2C_RDATA_REG_OFFSET, 0xef);
615
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500616 EXPECT_DIF_OK(dif_i2c_read_byte(&i2c_, &val));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400617 EXPECT_EQ(val, 0xab);
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500618 EXPECT_DIF_OK(dif_i2c_read_byte(&i2c_, &val));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400619 EXPECT_EQ(val, 0xcd);
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500620 EXPECT_DIF_OK(dif_i2c_read_byte(&i2c_, nullptr));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400621 EXPECT_EQ(val, 0xcd);
622}
623
624TEST_F(FifoTest, ReadNullArgs) {
625 uint8_t val;
Miguel Young de la Sotaf0896512022-03-10 14:17:42 -0500626 EXPECT_DIF_BADARG(dif_i2c_read_byte(nullptr, &val));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400627}
628
Drew Macrae8bf80122022-09-16 10:46:50 -0400629TEST_F(FifoTest, Acquire) {
630 uint8_t val;
631 dif_i2c_signal_t signal;
632
633 EXPECT_READ32(I2C_ACQDATA_REG_OFFSET, 0x0ab);
634 EXPECT_READ32(I2C_ACQDATA_REG_OFFSET, 0x3cd);
635 EXPECT_READ32(I2C_ACQDATA_REG_OFFSET, 0x2ef);
636 EXPECT_READ32(I2C_ACQDATA_REG_OFFSET, 0x101);
637
638 EXPECT_DIF_OK(dif_i2c_acquire_byte(&i2c_, &val, &signal));
639 EXPECT_EQ(val, 0xab);
640 EXPECT_EQ(signal, kDifI2cSignalNone);
641 EXPECT_DIF_OK(dif_i2c_acquire_byte(&i2c_, &val, &signal));
642 EXPECT_EQ(val, 0xcd);
643 EXPECT_EQ(signal, kDifI2cSignalRepeat);
644 EXPECT_DIF_OK(dif_i2c_acquire_byte(&i2c_, nullptr, &signal));
645 EXPECT_EQ(val, 0xcd);
646 EXPECT_EQ(signal, kDifI2cSignalStop);
647 EXPECT_DIF_OK(dif_i2c_acquire_byte(&i2c_, &val, nullptr));
648 EXPECT_EQ(val, 0x01);
649 EXPECT_EQ(signal, kDifI2cSignalStop);
650}
651
652TEST_F(FifoTest, AcqNullArgs) {
653 uint8_t val;
654 dif_i2c_signal_t signal;
655
656 EXPECT_DIF_BADARG(dif_i2c_acquire_byte(nullptr, &val, &signal));
657}
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400658
659TEST_F(FifoTest, WriteRaw) {
Miguel Young de la Sota4e1a4a32020-11-05 10:08:52 -0500660 EXPECT_WRITE32(I2C_FDATA_REG_OFFSET, {
661 {I2C_FDATA_FBYTE_OFFSET, 0x44},
662 {I2C_FDATA_START_BIT, 0x1},
663 });
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500664 EXPECT_DIF_OK(dif_i2c_write_byte_raw(&i2c_, 0x44,
665 {
666 .start = true,
667 }));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400668
669 EXPECT_WRITE32(I2C_FDATA_REG_OFFSET, {
670 {I2C_FDATA_FBYTE_OFFSET, 0x55},
671 });
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500672 EXPECT_DIF_OK(dif_i2c_write_byte_raw(&i2c_, 0x55, {}));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400673
674 EXPECT_WRITE32(I2C_FDATA_REG_OFFSET, {
675 {I2C_FDATA_FBYTE_OFFSET, 0x66},
Miguel Young de la Sota4e1a4a32020-11-05 10:08:52 -0500676 {I2C_FDATA_STOP_BIT, 0x1},
677 {I2C_FDATA_NAKOK_BIT, 0x1},
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400678 });
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500679 EXPECT_DIF_OK(dif_i2c_write_byte_raw(&i2c_, 0x66,
680 {
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500681 .stop = true,
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500682 .suppress_nak_irq = true,
683 }));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400684
685 EXPECT_WRITE32(I2C_FDATA_REG_OFFSET, {
686 {I2C_FDATA_FBYTE_OFFSET, 0x00},
Miguel Young de la Sota4e1a4a32020-11-05 10:08:52 -0500687 {I2C_FDATA_READ_BIT, 0x1},
688 {I2C_FDATA_RCONT_BIT, 0x1},
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400689 });
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500690 EXPECT_DIF_OK(dif_i2c_write_byte_raw(&i2c_, 0x00,
691 {
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500692 .read = true,
693 .read_cont = true,
694 }));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400695
Miguel Young de la Sota4e1a4a32020-11-05 10:08:52 -0500696 EXPECT_WRITE32(I2C_FDATA_REG_OFFSET, {
697 {I2C_FDATA_FBYTE_OFFSET, 0x77},
698 {I2C_FDATA_READ_BIT, 0x1},
699 });
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500700 EXPECT_DIF_OK(dif_i2c_write_byte_raw(&i2c_, 0x77,
701 {
Miguel Young de la Sota5129eab2022-03-10 14:15:51 -0500702 .read = true,
703 }));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400704}
705
706TEST_F(FifoTest, WriteRawBadArgs) {
Miguel Young de la Sotaf0896512022-03-10 14:17:42 -0500707 EXPECT_DIF_BADARG(dif_i2c_write_byte_raw(nullptr, 0xff, {}));
708 EXPECT_DIF_BADARG(dif_i2c_write_byte_raw(&i2c_, 0xff,
709 {
Timothy Chene53d5662022-09-06 16:42:33 -0700710 .start = true,
Miguel Young de la Sotaf0896512022-03-10 14:17:42 -0500711 .read = true,
712 }));
713 EXPECT_DIF_BADARG(dif_i2c_write_byte_raw(&i2c_, 0xff,
714 {
Miguel Young de la Sotaf0896512022-03-10 14:17:42 -0500715 .read_cont = true,
716 .suppress_nak_irq = true,
717 }));
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400718}
719
Drew Macrae8bf80122022-09-16 10:46:50 -0400720TEST_F(FifoTest, TransmitByte) {
721 EXPECT_WRITE32(I2C_TXDATA_REG_OFFSET, 0x00000044);
722 EXPECT_DIF_OK(dif_i2c_transmit_byte(&i2c_, 0x44));
723}
724
725TEST_F(FifoTest, TransmitBadArgs) {
726 EXPECT_DIF_BADARG(dif_i2c_transmit_byte(nullptr, 0xff));
727}
728
729class StretchTest : public I2cTest {};
730
731TEST_F(StretchTest, ConfigTimeouts) {
732 EXPECT_WRITE32(I2C_TIMEOUT_CTRL_REG_OFFSET, 0x81234567);
733 EXPECT_DIF_OK(dif_i2c_enable_clock_stretching_timeout(
734 &i2c_, kDifToggleEnabled, 0x01234567));
735 EXPECT_WRITE32(I2C_HOST_TIMEOUT_CTRL_REG_OFFSET, 0x81234567);
736 EXPECT_DIF_OK(dif_i2c_set_host_timeout(&i2c_, 0x81234567));
737}
738
739TEST_F(StretchTest, ConfigTimeoutsBadArgs) {
740 EXPECT_DIF_BADARG(dif_i2c_enable_clock_stretching_timeout(
741 nullptr, kDifToggleEnabled, 0x01234567));
742 EXPECT_DIF_BADARG(dif_i2c_set_host_timeout(nullptr, 0x81234567));
743}
744
Drew Macrae8bf80122022-09-16 10:46:50 -0400745// Assemble 2 Ids to the byte to form the expections checked in the address test
746uint32_t assemble_address(dif_i2c_id_t *id0, dif_i2c_id_t *id1) {
747 uint32_t config = 0x00000000;
748 if (id0 == NULL) {
749 config = bitfield_field32_write(config, I2C_TARGET_ID_ADDRESS0_FIELD, 0x7f);
750 } else {
751 config = bitfield_field32_write(config, I2C_TARGET_ID_ADDRESS0_FIELD,
752 id0->address);
753 config =
754 bitfield_field32_write(config, I2C_TARGET_ID_MASK0_FIELD, id0->mask);
755 }
756
757 if (id1 == NULL) {
758 config = bitfield_field32_write(config, I2C_TARGET_ID_ADDRESS1_FIELD, 0x7f);
759 } else {
760 config = bitfield_field32_write(config, I2C_TARGET_ID_ADDRESS1_FIELD,
761 id1->address);
762 config =
763 bitfield_field32_write(config, I2C_TARGET_ID_MASK1_FIELD, id1->mask);
764 }
765 return config;
766}
767
768class AddressTest : public I2cTest {};
769TEST_F(AddressTest, SetDeviceAddress) {
770 // dif_i2c_id_t id0 = NULL, id1 = NULL;
771 EXPECT_WRITE32(I2C_TARGET_ID_REG_OFFSET, assemble_address(nullptr, nullptr));
772 EXPECT_DIF_OK(dif_i2c_set_device_id(&i2c_, nullptr, nullptr));
773
774 dif_i2c_id_t id0 = {.mask = 0x12, .address = 0x34};
775 EXPECT_WRITE32(I2C_TARGET_ID_REG_OFFSET, assemble_address(&id0, nullptr));
776 EXPECT_DIF_OK(dif_i2c_set_device_id(&i2c_, &id0, nullptr));
777
778 dif_i2c_id_t id1 = {.mask = 0x56, .address = 0x78};
779 EXPECT_WRITE32(I2C_TARGET_ID_REG_OFFSET, assemble_address(nullptr, &id1));
780 EXPECT_DIF_OK(dif_i2c_set_device_id(&i2c_, nullptr, &id1));
781
782 EXPECT_WRITE32(I2C_TARGET_ID_REG_OFFSET, assemble_address(&id0, &id1));
783 EXPECT_DIF_OK(dif_i2c_set_device_id(&i2c_, &id0, &id1));
784}
785
786TEST_F(AddressTest, SetAddressBadArgs) {
787 dif_i2c_id_t id0, id1;
788 EXPECT_DIF_BADARG(dif_i2c_set_device_id(nullptr, &id0, &id1));
789}
790
Miguel Young de la Sota92bc4cc2020-04-09 12:32:43 -0400791} // namespace
792} // namespace dif_i2c_unittest