| Michael Schaffner | 74c4ff2 | 2021-03-30 15:43:46 -0700 | [diff] [blame] | 1 | CAPI=2: |
| 2 | # Copyright lowRISC contributors. |
| 3 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| 4 | # SPDX-License-Identifier: Apache-2.0 |
| 5 | |
| 6 | # TODO: long term this should be merged into AST. |
| 7 | |
| 8 | name: "lowrisc:systems:clkgen_xil7series" |
| 9 | description: "Clock generation infrastructure for Xilinx 7-Series FPGAs." |
| 10 | filesets: |
| 11 | files_rtl: |
| 12 | files: |
| 13 | - rtl/clkgen_xil7series.sv |
| Timothy Chen | a08273a | 2022-04-07 10:36:58 -0700 | [diff] [blame] | 14 | # piggy-back here for now |
| 15 | - rtl/usr_access_xil7series.sv |
| Michael Schaffner | 74c4ff2 | 2021-03-30 15:43:46 -0700 | [diff] [blame] | 16 | file_type: systemVerilogSource |
| 17 | |
| 18 | targets: |
| 19 | default: |
| 20 | filesets: |
| 21 | - files_rtl |
