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opensecura / 3p / lowrisc / opentitan / 961b2cdd2044ebaf354b2960aa0951e0ce353e33 / . / sw / vendor / patches / riscv_compliance / 0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch
blob: f454667f15a10b696f667cbaf38020da9c75c6d2 [file] [log] [blame]
Philipp Wagner70da3292020-09-21 17:25:35 +0100[diff] [blame]1From e8b82ff045fca264917a7c5539bfcbe8ed22b7a0 Mon Sep 17 00:00:00 2001
Greg Chadwickb22fb102020-04-16 14:30:04 +0100[diff] [blame]2From: Greg Chadwick <gac@lowrisc.org>
3Date: Wed, 15 Apr 2020 15:45:31 +0100
Michael Schaffner93fe50c2021-03-31 16:25:42 -0700[diff] [blame]4Subject: [PATCH 1/5] Add configurable trap alignment and entry point to p
Greg Chadwickb22fb102020-04-16 14:30:04 +0100[diff] [blame]5 test-env
6
Greg Chadwickb22fb102020-04-16 14:30:04 +0100[diff] [blame]7
8diff --git a/riscv-test-env/p/riscv_test.h b/riscv-test-env/p/riscv_test.h
9index eaa6758..9423523 100644
10--- a/riscv-test-env/p/riscv_test.h
11+++ b/riscv-test-env/p/riscv_test.h
12@@ -60,14 +60,14 @@
13 csrw pmpaddr0, t0; \
14 li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \
15 csrw pmpcfg0, t0; \
16- .align 2; \
17+ .align TRAPALIGN; \
18 1:
19
20 #define INIT_SPTBR \
21 la t0, 1f; \
22 csrw mtvec, t0; \
23 csrwi sptbr, 0; \
24- .align 2; \
25+ .align TRAPALIGN; \
26 1:
27
28 #define DELEGATE_NO_TRAPS \
29@@ -76,7 +76,7 @@
30 csrwi medeleg, 0; \
31 csrwi mideleg, 0; \
32 csrwi mie, 0; \
33- .align 2; \
34+ .align TRAPALIGN; \
35 1:
36
37 #define RVTEST_ENABLE_SUPERVISOR \
38@@ -125,6 +125,14 @@
39 #if defined(TRAPHANDLER)
40 #include TRAPHANDLER
41 #endif
42+#if !defined(TRAPALIGN)
43+#define TRAPALIGN 2
44+#endif
45+
46+#if !defined(RVTEST_ENTRY)
47+#define RVTEST_ENTRY _start
48+#endif
49+
50
51 #define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */
52
53@@ -133,11 +141,11 @@
54 .align 6; \
55 .weak stvec_handler; \
56 .weak mtvec_handler; \
57- .globl _start; \
58-_start: \
59+ .globl RVTEST_ENTRY; \
60+RVTEST_ENTRY: \
61 /* reset vector */ \
62 j reset_vector; \
63- .align 2; \
64+ .align TRAPALIGN; \
65 trap_vector: \
66 /* test whether the test came from pass/fail */ \
67 csrr t5, mcause; \
68diff --git a/riscv-test-suite/rv32i/src/I-EBREAK-01.S b/riscv-test-suite/rv32i/src/I-EBREAK-01.S
69index 958eebc..32c074c 100644
70--- a/riscv-test-suite/rv32i/src/I-EBREAK-01.S
71+++ b/riscv-test-suite/rv32i/src/I-EBREAK-01.S
72@@ -71,6 +71,7 @@ RV_COMPLIANCE_CODE_BEGIN
73
74 # ---------------------------------------------------------------------------------------------
75 # Exception handler
76+.align TRAPALIGN
77 _trap_handler:
78 # increment return address
79 csrr x30, mepc
80diff --git a/riscv-test-suite/rv32i/src/I-ECALL-01.S b/riscv-test-suite/rv32i/src/I-ECALL-01.S
81index 5278207..0bdee2a 100644
82--- a/riscv-test-suite/rv32i/src/I-ECALL-01.S
83+++ b/riscv-test-suite/rv32i/src/I-ECALL-01.S
84@@ -73,6 +73,7 @@ RV_COMPLIANCE_CODE_BEGIN
85
86 # ---------------------------------------------------------------------------------------------
87 # Exception handler
88+.align TRAPALIGN
89 _trap_handler:
90 # increment return address
91 csrr x30, mepc