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Tobias Wölfel8d8921e2020-05-12 10:32:19 +02001---
2title: "Reference Manuals"
3---
Garret Kelly9eebde02019-10-22 15:36:49 -04004
5* [Comportability Definition and Specification]({{< relref "comportability_specification" >}})
Sam Elliottb988cbc2020-04-20 19:56:54 +01006* [Device Interface Function (DIF) Specification]({{< relref "device_interface_functions" >}})
Garret Kelly9eebde02019-10-22 15:36:49 -04007* Tool Guides
Timothy Chen4bdc6f72019-10-31 15:44:45 -07008 * [Topgen Tool]({{< relref "topgen_tool" >}}): Describes `topgen.py` and its Hjson format source. Used to generate rtl and validation files for top specific modules such as PLIC, Pinmux and crossbar.
Eunchan Kimc8e630f2019-10-31 11:59:17 -07009 * [Register Tool]({{< relref "register_tool" >}}): Describes `regtool.py` and its Hjson format source. Used to generate documentation, rtl, header files and validation files for IP Registers and toplevel.
10 * [Crossbar Tool]({{< relref "crossbar_tool" >}}): Describes `tlgen.py` and its Hjson format source. Used to generate self-documentation, rtl files of the crossbars at the toplevel.
Miguel Osorioba17f112019-11-15 12:30:14 -080011 * [Vendor-In Tool]({{< relref "vendor_in_tool" >}}): Describes `util/vendor.py` and its Hjson control file. Used to pull a local copy of code maintained in other upstream repositories and apply local patch sets.
Garret Kelly9eebde02019-10-22 15:36:49 -040012* Coding Style Guides
13 * [Verilog Coding Style](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md)
14 * [Python Coding Style]({{< relref "python_coding_style.md" >}})
15 * [Hjson Usage and Style Guide]({{< relref "hjson_usage_style.md" >}})
16 * [Markdown Usage and Style Guide]({{< relref "markdown_usage_style.md" >}})
17 * [C/C++ Style Guide]({{< relref "c_cpp_coding_style.md" >}})
Miguel Young de la Sota6d335d72019-11-07 13:55:02 -060018 * [RISC-V Assembly Style Guide]({{< relref "asm_coding_style.md" >}})
Michael Schaffnerb23eccd2019-11-07 11:34:27 -080019* [FPGA Reference Manual]({{< relref "ref_manual_fpga.md" >}})