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opensecura / 3p / lowrisc / opentitan / 87fb9e3273b57bad8a662a96dcfb7d5c0e22b0ff / . / util / uvmdvgen / checklist.md.tpl
blob: 187dda700d43acfeea8d4861220fe155e0cfa97f [file] [log] [blame]
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]1---
2title: "${name.upper()} Checklist"
3---
4
Srikrishna Iyerd1f896e2020-03-05 13:52:40 -0800[diff] [blame]5<!--
6NOTE: This is a template checklist document that is required to be copied over to the 'doc'
7directory for a new design that transitions from L0 (Specification) to L1 (Development)
8stage, and updated as needed. Once done, please remove this comment before checking it in.
9-->
Philipp Wagner5bf19db2021-03-18 15:40:08 +0000[diff] [blame]10This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [${name.upper()} peripheral.]({{< relref "." >}})
Scott Johnson8573fa22019-11-01 14:49:56 -0700[diff] [blame]11All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]12
Philipp Wagner1d9fc212020-09-17 10:48:36 +0100[diff] [blame]13<%text>## Design Checklist</%text>
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]14
Philipp Wagner1d9fc212020-09-17 10:48:36 +0100[diff] [blame]15<%text>### D1</%text>
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]16
Scott Johnson1fba1552020-10-12 23:18:58 -0700[diff] [blame]17Type | Item | Resolution | Note/Collaterals
18--------------|--------------------------------|-------------|------------------
Philipp Wagner5bf19db2021-03-18 15:40:08 +0000[diff] [blame]19Documentation | [SPEC_COMPLETE][] | Not Started | [${name.upper()} Design Spec]({{<relref "." >}})
Scott Johnson1fba1552020-10-12 23:18:58 -0700[diff] [blame]20Documentation | [CSR_DEFINED][] | Not Started |
21RTL | [CLKRST_CONNECTED][] | Not Started |
22RTL | [IP_TOP][] | Not Started |
23RTL | [IP_INSTANTIABLE][] | Not Started |
24RTL | [PHYSICAL_MACROS_DEFINED_80][] | Not Started |
25RTL | [FUNC_IMPLEMENTED][] | Not Started |
26RTL | [ASSERT_KNOWN_ADDED][] | Not Started |
27Code Quality | [LINT_SETUP][] | Not Started |
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]28
Scott Johnson1fba1552020-10-12 23:18:58 -0700[diff] [blame]29[SPEC_COMPLETE]: {{<relref "/doc/project/checklist.md#spec_complete" >}}
30[CSR_DEFINED]: {{<relref "/doc/project/checklist.md#csr_defined" >}}
31[CLKRST_CONNECTED]: {{<relref "/doc/project/checklist.md#clkrst_connected" >}}
32[IP_TOP]: {{<relref "/doc/project/checklist.md#ip_top" >}}
33[IP_INSTANTIABLE]: {{<relref "/doc/project/checklist.md#ip_instantiable" >}}
34[PHYSICAL_MACROS_DEFINED_80]: {{<relref "/doc/project/checklist.md#physical_macros_defined_80" >}}
35[FUNC_IMPLEMENTED]: {{<relref "/doc/project/checklist.md#func_implemented" >}}
36[ASSERT_KNOWN_ADDED]: {{<relref "/doc/project/checklist.md#assert_known_added" >}}
37[LINT_SETUP]: {{<relref "/doc/project/checklist.md#lint_setup" >}}
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]38
Philipp Wagner1d9fc212020-09-17 10:48:36 +0100[diff] [blame]39<%text>### D2</%text>
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]40
41Type | Item | Resolution | Note/Collaterals
42--------------|-------------------------|-------------|------------------
Scott Johnson8573fa22019-11-01 14:49:56 -0700[diff] [blame]43Documentation | [NEW_FEATURES][] | Not Started |
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]44Documentation | [BLOCK_DIAGRAM][] | Not Started |
45Documentation | [DOC_INTERFACE][] | Not Started |
46Documentation | [MISSING_FUNC][] | Not Started |
47Documentation | [FEATURE_FROZEN][] | Not Started |
48RTL | [FEATURE_COMPLETE][] | Not Started |
Cindy Chen432430e2020-11-12 09:51:50 -0800[diff] [blame]49RTL | [AREA_CHECK][] | Not Started |
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]50RTL | [PORT_FROZEN][] | Not Started |
51RTL | [ARCHITECTURE_FROZEN][] | Not Started |
52RTL | [REVIEW_TODO][] | Not Started |
53RTL | [STYLE_X][] | Not Started |
54Code Quality | [LINT_PASS][] | Not Started |
55Code Quality | [CDC_SETUP][] | Not Started |
56Code Quality | [FPGA_TIMING][] | Not Started |
57Code Quality | [CDC_SYNCMACRO][] | Not Started |
Scott Johnsonbd8a6902020-06-24 09:12:42 -0700[diff] [blame]58Security | [SEC_CM_IMPLEMENTED][] | Not Started |
59Security | [SEC_NON_RESET_FLOPS][] | Not Started |
60Security | [SEC_SHADOW_REGS][] | Not Started |
Michael Schaffnere80c0c42020-11-03 14:48:57 -0800[diff] [blame]61Security | [SEC_RND_CNST][] | Not Started |
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]62
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]63[NEW_FEATURES]: {{<relref "/doc/project/checklist.md#new_features" >}}
64[BLOCK_DIAGRAM]: {{<relref "/doc/project/checklist.md#block_diagram" >}}
65[DOC_INTERFACE]: {{<relref "/doc/project/checklist.md#doc_interface" >}}
66[MISSING_FUNC]: {{<relref "/doc/project/checklist.md#missing_func" >}}
67[FEATURE_FROZEN]: {{<relref "/doc/project/checklist.md#feature_frozen" >}}
68[FEATURE_COMPLETE]: {{<relref "/doc/project/checklist.md#feature_complete" >}}
Cindy Chen432430e2020-11-12 09:51:50 -0800[diff] [blame]69[AREA_CHECK]: {{<relref "/doc/project/checklist.md#area_check" >}}
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]70[PORT_FROZEN]: {{<relref "/doc/project/checklist.md#port_frozen" >}}
71[ARCHITECTURE_FROZEN]: {{<relref "/doc/project/checklist.md#architecture_frozen" >}}
72[REVIEW_TODO]: {{<relref "/doc/project/checklist.md#review_todo" >}}
73[STYLE_X]: {{<relref "/doc/project/checklist.md#style_x" >}}
74[LINT_PASS]: {{<relref "/doc/project/checklist.md#lint_pass" >}}
75[CDC_SETUP]: {{<relref "/doc/project/checklist.md#cdc_setup" >}}
76[FPGA_TIMING]: {{<relref "/doc/project/checklist.md#fpga_timing" >}}
77[CDC_SYNCMACRO]: {{<relref "/doc/project/checklist.md#cdc_syncmacro" >}}
78[SEC_CM_IMPLEMENTED]: {{<relref "/doc/project/checklist.md#sec_cm_implemented" >}}
79[SEC_NON_RESET_FLOPS]: {{<relref "/doc/project/checklist.md#sec_non_reset_flops" >}}
80[SEC_SHADOW_REGS]: {{<relref "/doc/project/checklist.md#sec_shadow_regs" >}}
Michael Schaffnere80c0c42020-11-03 14:48:57 -0800[diff] [blame]81[SEC_RND_CNST]: {{<relref "/doc/project/checklist.md#sec_rnd_cnst" >}}
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]82
Philipp Wagner1d9fc212020-09-17 10:48:36 +0100[diff] [blame]83<%text>### D3</%text>
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]84
85 Type | Item | Resolution | Note/Collaterals
86--------------|-------------------------|-------------|------------------
87Documentation | [NEW_FEATURES_D3][] | Not Started |
88RTL | [TODO_COMPLETE][] | Not Started |
89Code Quality | [LINT_COMPLETE][] | Not Started |
90Code Quality | [CDC_COMPLETE][] | Not Started |
91Review | [REVIEW_RTL][] | Not Started |
92Review | [REVIEW_DELETED_FF][] | Not Started |
93Review | [REVIEW_SW_CSR][] | Not Started |
94Review | [REVIEW_SW_FATAL_ERR][] | Not Started |
95Review | [REVIEW_SW_CHANGE][] | Not Started |
96Review | [REVIEW_SW_ERRATA][] | Not Started |
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]97Review | Reviewer(s) | Not Started |
98Review | Signoff date | Not Started |
99
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]100[NEW_FEATURES_D3]: {{<relref "/doc/project/checklist.md#new_features_d3" >}}
101[TODO_COMPLETE]: {{<relref "/doc/project/checklist.md#todo_complete" >}}
102[LINT_COMPLETE]: {{<relref "/doc/project/checklist.md#lint_complete" >}}
103[CDC_COMPLETE]: {{<relref "/doc/project/checklist.md#cdc_complete" >}}
104[REVIEW_RTL]: {{<relref "/doc/project/checklist.md#review_rtl" >}}
105[REVIEW_DBG]: {{<relref "/doc/project/checklist.md#review_dbg" >}}
106[REVIEW_DELETED_FF]: {{<relref "/doc/project/checklist.md#review_deleted_ff" >}}
107[REVIEW_SW_CSR]: {{<relref "/doc/project/checklist.md#review_sw_csr" >}}
108[REVIEW_SW_FATAL_ERR]: {{<relref "/doc/project/checklist.md#review_sw_fatal_err" >}}
109[REVIEW_SW_CHANGE]: {{<relref "/doc/project/checklist.md#review_sw_change" >}}
110[REVIEW_SW_ERRATA]: {{<relref "/doc/project/checklist.md#review_sw_errata" >}}
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]111
Philipp Wagner1d9fc212020-09-17 10:48:36 +0100[diff] [blame]112<%text>## Verification Checklist</%text>
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]113
Philipp Wagner1d9fc212020-09-17 10:48:36 +0100[diff] [blame]114<%text>### V1</%text>
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]115
116 Type | Item | Resolution | Note/Collaterals
117--------------|---------------------------------------|-------------|------------------
Srikrishna Iyer600230a2021-05-14 14:26:53 -0700[diff] [blame]118Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [${name.upper()} DV document]({{<relref "dv" >}})
119Documentation | [TESTPLAN_COMPLETED][] | Not Started | [${name.upper()} Testplan]({{<relref "dv/index.md#testplan" >}})
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]120Testbench | [TB_TOP_CREATED][] | Not Started |
121Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started |
Pirmin Vogel4fc23302020-03-13 12:12:15 +0100[diff] [blame]122Testbench | [SIM_TB_ENV_CREATED][] | Not Started |
123Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Not Started |
124Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Not Started |
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]125Testbench | [TB_GEN_AUTOMATED][] | Not Started |
Cindy Chene513e362020-11-11 10:28:54 -0800[diff] [blame]126Tests | [SIM_SMOKE_TEST_PASSING][] | Not Started |
Pirmin Vogel4fc23302020-03-13 12:12:15 +0100[diff] [blame]127Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Not Started |
128Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | Not Started |
129Tool Setup | [SIM_ALT_TOOL_SETUP][] | Not Started |
Cindy Chene513e362020-11-11 10:28:54 -0800[diff] [blame]130Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Not Started |
Pirmin Vogel4fc23302020-03-13 12:12:15 +0100[diff] [blame]131Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Not Started |
132Regression | [FPV_REGRESSION_SETUP][] | Not Started |
133Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Not Started |
Cindy Chenb811dac2020-11-04 10:32:54 -0800[diff] [blame]134Code Quality | [TB_LINT_SETUP][] | Not Started |
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]135Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Not Started |
136Review | [DESIGN_SPEC_REVIEWED][] | Not Started |
Srikrishna Iyer600230a2021-05-14 14:26:53 -0700[diff] [blame]137Review | [TESTPLAN_REVIEWED][] | Not Started |
Pirmin Vogel4fc23302020-03-13 12:12:15 +0100[diff] [blame]138Review | [STD_TEST_CATEGORIES_PLANNED][] | Not Started | Exception (?)
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]139Review | [V2_CHECKLIST_SCOPED][] | Not Started |
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]140
Michael Schaffnerb773efa2020-12-11 15:11:55 -0800[diff] [blame]141[DV_DOC_DRAFT_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_doc_draft_completed" >}}
Srikrishna Iyer600230a2021-05-14 14:26:53 -0700[diff] [blame]142[TESTPLAN_COMPLETED]: {{<relref "/doc/project/checklist.md#testplan_completed" >}}
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]143[TB_TOP_CREATED]: {{<relref "/doc/project/checklist.md#tb_top_created" >}}
144[PRELIMINARY_ASSERTION_CHECKS_ADDED]: {{<relref "/doc/project/checklist.md#preliminary_assertion_checks_added" >}}
145[SIM_TB_ENV_CREATED]: {{<relref "/doc/project/checklist.md#sim_tb_env_created" >}}
146[SIM_RAL_MODEL_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#sim_ral_model_gen_automated" >}}
147[CSR_CHECK_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#csr_check_gen_automated" >}}
148[TB_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#tb_gen_automated" >}}
Cindy Chene513e362020-11-11 10:28:54 -0800[diff] [blame]149[SIM_SMOKE_TEST_PASSING]: {{<relref "/doc/project/checklist.md#sim_smoke_test_passing" >}}
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]150[SIM_CSR_MEM_TEST_SUITE_PASSING]: {{<relref "/doc/project/checklist.md#sim_csr_mem_test_suite_passing" >}}
151[FPV_MAIN_ASSERTIONS_PROVEN]: {{<relref "/doc/project/checklist.md#fpv_main_assertions_proven" >}}
152[SIM_ALT_TOOL_SETUP]: {{<relref "/doc/project/checklist.md#sim_alt_tool_setup" >}}
Cindy Chene513e362020-11-11 10:28:54 -0800[diff] [blame]153[SIM_SMOKE_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#sim_smoke_regression_setup" >}}
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]154[SIM_NIGHTLY_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#sim_nightly_regression_setup" >}}
155[FPV_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#fpv_regression_setup" >}}
156[SIM_COVERAGE_MODEL_ADDED]: {{<relref "/doc/project/checklist.md#sim_coverage_model_added" >}}
Cindy Chenb811dac2020-11-04 10:32:54 -0800[diff] [blame]157[TB_LINT_SETUP]: {{<relref "/doc/project/checklist.md#tb_lint_setup" >}}
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]158[PRE_VERIFIED_SUB_MODULES_V1]: {{<relref "/doc/project/checklist.md#pre_verified_sub_modules_v1" >}}
159[DESIGN_SPEC_REVIEWED]: {{<relref "/doc/project/checklist.md#design_spec_reviewed" >}}
Srikrishna Iyer600230a2021-05-14 14:26:53 -0700[diff] [blame]160[TESTPLAN_REVIEWED]: {{<relref "/doc/project/checklist.md#testplan_reviewed" >}}
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]161[STD_TEST_CATEGORIES_PLANNED]: {{<relref "/doc/project/checklist.md#std_test_categories_planned" >}}
162[V2_CHECKLIST_SCOPED]: {{<relref "/doc/project/checklist.md#v2_checklist_scoped" >}}
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]163
Philipp Wagner1d9fc212020-09-17 10:48:36 +0100[diff] [blame]164<%text>### V2</%text>
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]165
166 Type | Item | Resolution | Note/Collaterals
167--------------|-----------------------------------------|-------------|------------------
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]168Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Not Started |
Srikrishna Iyer600230a2021-05-14 14:26:53 -0700[diff] [blame]169Documentation | [DV_DOC_COMPLETED][] | Not Started |
170Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Not Started |
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]171Testbench | [ALL_INTERFACES_EXERCISED][] | Not Started |
172Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Not Started |
173Testbench | [SIM_TB_ENV_COMPLETED][] | Not Started |
174Tests | [SIM_ALL_TESTS_PASSING][] | Not Started |
175Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | Not Started |
176Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | Not Started |
177Tests | [SIM_FW_SIMULATED][] | Not Started |
178Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Not Started |
179Coverage | [SIM_CODE_COVERAGE_V2][] | Not Started |
180Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Not Started |
181Coverage | [FPV_CODE_COVERAGE_V2][] | Not Started |
182Coverage | [FPV_COI_COVERAGE_V2][] | Not Started |
Cindy Chenb811dac2020-11-04 10:32:54 -0800[diff] [blame]183Code Quality | [TB_LINT_PASS][] | Not Started |
Srikrishna Iyer600230a2021-05-14 14:26:53 -0700[diff] [blame]184Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Not Started |
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]185Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Not Started |
186Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Not Started |
Srikrishna Iyer600230a2021-05-14 14:26:53 -0700[diff] [blame]187Review | [DV_DOC_TESTPLAN_REVIEWED][] | Not Started |
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]188Review | [V3_CHECKLIST_SCOPED][] | Not Started |
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]189
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]190[DESIGN_DELTAS_CAPTURED_V2]: {{<relref "/doc/project/checklist.md#design_deltas_captured_v2" >}}
Srikrishna Iyer600230a2021-05-14 14:26:53 -0700[diff] [blame]191[DV_DOC_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_doc_completed" >}}
192[FUNCTIONAL_COVERAGE_IMPLEMENTED]: {{<relref "/doc/project/checklist.md#functional_coverage_implemented" >}}
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]193[ALL_INTERFACES_EXERCISED]: {{<relref "/doc/project/checklist.md#all_interfaces_exercised" >}}
194[ALL_ASSERTION_CHECKS_ADDED]: {{<relref "/doc/project/checklist.md#all_assertion_checks_added" >}}
195[SIM_TB_ENV_COMPLETED]: {{<relref "/doc/project/checklist.md#sim_tb_env_completed" >}}
196[SIM_ALL_TESTS_PASSING]: {{<relref "/doc/project/checklist.md#sim_all_tests_passing" >}}
197[FPV_ALL_ASSERTIONS_WRITTEN]: {{<relref "/doc/project/checklist.md#fpv_all_assertions_written" >}}
198[FPV_ALL_ASSUMPTIONS_REVIEWED]: {{<relref "/doc/project/checklist.md#fpv_all_assumptions_reviewed" >}}
199[SIM_FW_SIMULATED]: {{<relref "/doc/project/checklist.md#sim_fw_simulated" >}}
200[SIM_NIGHTLY_REGRESSION_V2]: {{<relref "/doc/project/checklist.md#sim_nightly_regression_v2" >}}
201[SIM_CODE_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#sim_code_coverage_v2" >}}
202[SIM_FUNCTIONAL_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#sim_functional_coverage_v2" >}}
203[FPV_CODE_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#fpv_code_coverage_v2" >}}
204[FPV_COI_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#fpv_coi_coverage_v2" >}}
Cindy Chenb811dac2020-11-04 10:32:54 -0800[diff] [blame]205[TB_LINT_PASS]: {{<relref "/doc/project/checklist.md#tb_lint_pass" >}}
Srikrishna Iyer600230a2021-05-14 14:26:53 -0700[diff] [blame]206[PRE_VERIFIED_SUB_MODULES_V2]: {{<relref "/doc/project/checklist.md#pre_verified_sub_modules_v2" >}}
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]207[NO_HIGH_PRIORITY_ISSUES_PENDING]: {{<relref "/doc/project/checklist.md#no_high_priority_issues_pending" >}}
208[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:{{<relref "/doc/project/checklist.md#all_low_priority_issues_root_caused" >}}
Srikrishna Iyer600230a2021-05-14 14:26:53 -0700[diff] [blame]209[DV_DOC_TESTPLAN_REVIEWED]: {{<relref "/doc/project/checklist.md#dv_doc_testplan_reviewed" >}}
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]210[V3_CHECKLIST_SCOPED]: {{<relref "/doc/project/checklist.md#v3_checklist_scoped" >}}
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]211
Philipp Wagner1d9fc212020-09-17 10:48:36 +0100[diff] [blame]212<%text>### V3</%text>
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]213
214 Type | Item | Resolution | Note/Collaterals
215--------------|-----------------------------------|-------------|------------------
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]216Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started |
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]217Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started |
218Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started |
219Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started |
220Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started |
221Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started |
222Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started |
223Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started |
Srikrishna Iyer600230a2021-05-14 14:26:53 -0700[diff] [blame]224Code Quality | [ALL_TODOS_RESOLVED][] | Not Started |
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]225Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started |
Cindy Chenb811dac2020-11-04 10:32:54 -0800[diff] [blame]226Code Quality | [TB_LINT_COMPLETE][] | Not Started |
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]227Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started |
Srikrishna Iyer600230a2021-05-14 14:26:53 -0700[diff] [blame]228Issues | [NO_ISSUES_PENDING][] | Not Started |
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]229Review | Reviewer(s) | Not Started |
230Review | Signoff date | Not Started |
Eunchan Kimcce72b62019-10-28 23:23:40 -0700[diff] [blame]231
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]232[DESIGN_DELTAS_CAPTURED_V3]: {{<relref "/doc/project/checklist.md#design_deltas_captured_v3" >}}
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]233[X_PROP_ANALYSIS_COMPLETED]: {{<relref "/doc/project/checklist.md#x_prop_analysis_completed" >}}
234[FPV_ASSERTIONS_PROVEN_AT_V3]: {{<relref "/doc/project/checklist.md#fpv_assertions_proven_at_v3" >}}
235[SIM_NIGHTLY_REGRESSION_AT_V3]: {{<relref "/doc/project/checklist.md#sim_nightly_regression_at_v3" >}}
236[SIM_CODE_COVERAGE_AT_100]: {{<relref "/doc/project/checklist.md#sim_code_coverage_at_100" >}}
237[SIM_FUNCTIONAL_COVERAGE_AT_100]:{{<relref "/doc/project/checklist.md#sim_functional_coverage_at_100" >}}
238[FPV_CODE_COVERAGE_AT_100]: {{<relref "/doc/project/checklist.md#fpv_code_coverage_at_100" >}}
239[FPV_COI_COVERAGE_AT_100]: {{<relref "/doc/project/checklist.md#fpv_coi_coverage_at_100" >}}
Srikrishna Iyer600230a2021-05-14 14:26:53 -0700[diff] [blame]240[ALL_TODOS_RESOLVED]: {{<relref "/doc/project/checklist.md#all_todos_resolved" >}}
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]241[NO_TOOL_WARNINGS_THROWN]: {{<relref "/doc/project/checklist.md#no_tool_warnings_thrown" >}}
Cindy Chenb811dac2020-11-04 10:32:54 -0800[diff] [blame]242[TB_LINT_COMPLETE]: {{<relref "/doc/project/checklist.md#tb_lint_complete" >}}
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]243[PRE_VERIFIED_SUB_MODULES_V3]: {{<relref "/doc/project/checklist.md#pre_verified_sub_modules_v3" >}}
Srikrishna Iyer600230a2021-05-14 14:26:53 -0700[diff] [blame]244[NO_ISSUES_PENDING]: {{<relref "/doc/project/checklist.md#no_issues_pending" >}}