| Garret Kelly | 9eebde0 | 2019-10-22 15:36:49 -0400 | [diff] [blame] | 1 | # Hardware Specifications |
| 2 | |
| 3 | This is the landing spot for all hardware specifications within the OpenTitan project. |
| 4 | This includes: top level specification(s); processor core(s) specifications; and [Comportable IP]({{< relref "doc/rm/comportability_specification" >}}) specifications. |
| 5 | |
| 6 | ## Available Top Level Specifications |
| 7 | |
| 8 | * [`top_earlgrey` design specification]({{< relref "hw/top_earlgrey/doc" >}}) |
| 9 | |
| 10 | ## Available Processor Core Specifications |
| 11 | |
| 12 | * [`core_ibex` user manual](https://ibex-core.readthedocs.io/en/latest) |
| 13 | |
| 14 | ## Available Comportable IP Block Design Specifications and Verification Plans |
| 15 | |
| 16 | | Module | Design Spec | DV Plan | |
| 17 | |--------|-------------|---------| |
| 18 | | aes | [design spec]({{< relref "hw/ip/aes/doc" >}}) |
| 19 | | alert\_handler | [design spec]({{< relref "hw/ip/alert_handler/doc" >}}) |
| 20 | | entropy\_src | |
| 21 | | flash\_ctrl | [design spec]({{< relref "hw/ip/flash_ctrl/doc" >}}) |
| 22 | | gpio | [design spec]({{< relref "hw/ip/gpio/doc" >}}) | [DV plan]({{< relref "hw/ip/gpio/doc/dv_plan" >}}) |
| 23 | | hmac | [design spec]({{< relref "hw/ip/hmac/doc" >}}) | [DV plan]({{< relref "hw/ip/hmac/doc/dv_plan" >}}) |
| 24 | | i2c | | [DV plan]({{< relref "hw/ip/i2c/doc/dv_plan" >}}) |
| 25 | | padctrl |[design spec]({{< relref "hw/ip/padctrl/doc" >}}) |
| 26 | | pinmux |[design spec]({{< relref "hw/ip/pinmux/doc" >}}) |
| 27 | | rv\_core\_ibex |[design spec]({{< relref "hw/ip/rv_core_ibex/doc" >}}) |
| 28 | | rv\_dm |[design spec]({{< relref "hw/ip/rv_dm/doc" >}}) |
| 29 | | rv\_plic |[design spec]({{< relref "hw/ip/rv_plic/doc" >}}) |
| 30 | | rv\_timer |[design spec]({{< relref "hw/ip/rv_timer/doc" >}}) | [DV plan]({{< relref "hw/ip/rv_timer/doc/dv_plan" >}}) |
| 31 | | spi\_device |[design spec]({{< relref "hw/ip/spi_device/doc" >}}) |
| 32 | | tlul |[design spec]({{< relref "hw/ip/tlul/doc" >}}) |
| 33 | | uart |[design spec]({{< relref "hw/ip/uart/doc" >}}) | [DV plan]({{< relref "hw/ip/uart/doc/dv_plan" >}}) |
