blob: 4a116ff10342b243837c8e611ebd40fdf25ce340 [file] [log] [blame]
Eunchan Kim06550352020-10-12 16:42:45 -07001# Copyright lowRISC contributors.
2# Licensed under the Apache License, Version 2.0, see LICENSE for details.
3# SPDX-License-Identifier: Apache-2.0
4#
5# Rules for svlint, a SystemVerilog linter commonly used in editors.
6# The configuration matches the lowRISC SystemVerilog style guide at
7# https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md.
8# See https://github.com/dalance/svlint/blob/master/RULES.md for a list of rules.
9
10[option]
11exclude_paths = ["build.*", "sw/.*", ".sv.tpl$"]
12
13[rules]
Eunchan Kim0445f012021-05-27 04:11:55 -070014blocking_assignment_in_always_ff = true
Eunchan Kim06550352020-10-12 16:42:45 -070015case_default = true
Eunchan Kim0445f012021-05-27 04:11:55 -070016default_nettype_none = false
Eunchan Kim06550352020-10-12 16:42:45 -070017enum_with_type = true
18for_with_begin = true
19function_same_as_system_function = true
20function_with_automatic = true
21generate_for_with_label = true
22generate_if_with_label = true
23generate_keyword_forbidden = true
24generate_keyword_required = false
25genvar_declaration_in_loop = true
26genvar_declaration_out_loop = false
27if_with_begin = true
28inout_with_tri = false
29input_with_var = false
30interface_port_with_modport = false
31legacy_always = false
32level_sensitive_always = true
33loop_variable_declaration = true
34non_ansi_module = true
Eunchan Kim0445f012021-05-27 04:11:55 -070035non_blocking_assignment_in_always_comb = true
Eunchan Kim06550352020-10-12 16:42:45 -070036output_with_var = false
37parameter_in_package = false
Eunchan Kim0445f012021-05-27 04:11:55 -070038priority_keyword = false
Eunchan Kim06550352020-10-12 16:42:45 -070039tab_character = true
40unique0_keyword = false
41unique_keyword = false
42wire_reg = true