blob: 98411e568da683cbdf439d95a7164e916c79a16f [file] [log] [blame]
Will Chen4af6c252020-03-12 11:30:59 -07001# Copyright lowRISC contributors.
2# Licensed under the Apache License, Version 2.0, see LICENSE for details.
3# SPDX-License-Identifier: Apache-2.0
4
5# This script has commands to run the design using VC Formal
6
7#-------------------------------------------------------------------------
8# Analysing and elaborating the design
9#-------------------------------------------------------------------------
10# only one scr file exists in this folder
11
12analyze -format sverilog \
13 -vcs "+define+FPV_ON -assert svaext \
Will Chen4af6c252020-03-12 11:30:59 -070014 -f [glob *.scr]"
15
Cindy Chenc37f6972020-06-24 14:25:02 -070016elaborate -sva $env(FPV_TOP)
Will Chen4af6c252020-03-12 11:30:59 -070017
18#-------------------------------------------------------------------------
19# Specify clock(s) and reset(s)
20#-------------------------------------------------------------------------
21# specify the primary clocks and resets in the design.
22# use "-period" option with "create_clock" to specify the period
23# use "-sense low/high" option with "create_reset" to specify active low or high reset respectively
24#
25# note: the TL-UL protocol checker tlul_assert.sv operates on the negedge clock
26
27if {$env(FPV_TOP) == "rv_dm"} {
Cindy Chenc37f6972020-06-24 14:25:02 -070028 create_clock clk_i -period 100
Will Chen4af6c252020-03-12 11:30:59 -070029 create_clock tck_i -period 100
30 create_reset rst_ni -sense low
31 create_reset trst_ni -sense low
32} elseif {$env(FPV_TOP) == "spi_device"} {
33 create_clock clk_i -period 100
34 create_clock cio_sck_i -period 100
35 create_reset rst_ni -sense low
Cindy Chenc37f6972020-06-24 14:25:02 -070036 create_reset cio_csb_i -sense high
Will Chen4af6c252020-03-12 11:30:59 -070037} elseif {$env(FPV_TOP) == "usb_fs_nb_pe"} {
38 create_clock clk_48mhz_i -period 100
Cindy Chenc37f6972020-06-24 14:25:02 -070039 create_reset rst_ni -sense low
Will Chen4af6c252020-03-12 11:30:59 -070040} elseif {$env(FPV_TOP) == "usbuart"} {
41 create_clock clk_i -period 100
Cindy Chenc37f6972020-06-24 14:25:02 -070042 create_clock clk_48mhz_i -period 100
Will Chen4af6c252020-03-12 11:30:59 -070043 create_reset rst_ni -sense low
44} elseif {$env(FPV_TOP) == "usbdev"} {
45 create_clock clk_i -period 100
46 create_clock clk_usb_48mhz_i -period 100
47 create_reset rst_ni -sense low
48} elseif {$env(FPV_TOP) == "top_earlgrey"} {
49 create_clock clk_i -period 100
50 create_clock jtag_tck_i -period 100
51 create_reset rst_ni -sense low
52 create_reset jtag_trst_ni -sense low
53} elseif {$env(FPV_TOP) == "xbar_main"} {
54 create_clock clk_main_i -period 100
55 create_reset rst_main_ni -sense low
56} else {
57 create_clock clk_i -period 100
58 create_reset rst_ni -sense low
59}
60
61#-------------------------------------------------------------------------
62# Assume properties for inputs
63#-------------------------------------------------------------------------
64
65# For sram2tlul, input tl_i.a_ready is constrained by below asssertion
66fvassume sram2tlul.validNotReady*
67
68# Input scanmode_i should not be X
69fvassume *.scanmodeKnown
70
71#-------------------------------------------------------------------------
72# TODO: eventually remove below assert disable lines
73# To reduce prohibitive runtimes, below assertions are simply turned off for now
74#-------------------------------------------------------------------------
75
76# spi_device
77fvdisable {*spi_device.u_tlul2sram.tlul_assert_host.responseSize*}
78fvdisable {*spi_device.u_tlul2sram.tlul_assert_host.onlyOnePendingReq*}
79fvdisable {*spi_device.tlul_assert_host.responseMustHaveReq*}
80fvdisable {*spi_device.tlul_assert_host.checkResponseOpcode*}
81fvdisable {*spi_device.u_reg.tlul_assert_host.responseMustHaveReq*}
82fvdisable {*spi_device.u_reg.tlul_assert_host.checkResponseOpcode*}
83fvdisable {*spi_device.u_reg.u_socket.tlul_assert_host.responseMustHaveReq*}
84fvdisable {*spi_device.u_reg.u_socket.tlul_assert_host.checkResponseOpcode*}
85fvdisable {*spi_device.u_reg.u_socket.tlul_assert_device.gen_assert*.tlul_assert.responseSize*}
86fvdisable {*spi_device.u_reg.u_socket.tlul_assert_device.gen_assert*.tlul_assert.onlyOnePendingReq*}
87fvdisable {*spi_device.u_reg.u_socket.tlul_assert_host.responseSizeMustEqualReq*}
88fvdisable {*spi_device.tlul_assert_host.responseSizeMustEqualReq*}
89
90# hmac
91fvdisable {*hmac.u_tlul_adapter.tlul_assert_host.onlyOnePendingReq*}
92fvdisable {*hmac.u_reg.u_socket.tlul_assert_device.gen_assert[0]*onlyOnePendingReq*}
93
94# flash_ctrl
95fvdisable {*flash_ctrl.tlul_assert_host.response*Must*}
96fvdisable {*flash_ctrl.u_reg.u_socket.tlul_assert_*.response*Must*}
97fvdisable {*flash_ctrl.u_reg.u_socket.tlul_assert_device.gen_assert*.tlul_assert.onlyOnePendingReq*}
98
99# xbar
100fvdisable {*xbar_main.tlul_assert_device_*.sizeMatches*}
101fvdisable {*xbar_main.tlul_assert_device_*.legalA*}
102fvdisable {*xbar_main.tlul_assert_device_*.addressAligned*}
103fvdisable {*xbar_main.tlul_assert_device_*.maskMustBeCont*}
104fvdisable {*xbar_main.tlul_assert_host_*.legal*}
105fvdisable {*xbar_main.u_*.tlul_assert_host.legalDParam*}
106fvdisable {*xbar_main.u_*.tlul_assert_device.response*}
107fvdisable {*xbar_main.u_*.tlul_assert_device.legalA*}
108fvdisable {*xbar_main.u_*.tlul_assert_device.addressAligned*}
109fvdisable {*xbar_main.u_*.tlul_assert_device.checkResponseOp*}
110fvdisable {*xbar_main.u_*.tlul_assert_device.maskMustBeCont*}
111fvdisable {*xbar_main.u_*.tlul_assert_device.sizeMatches*}
112fvdisable {*xbar_main.u_*.tlul_assert_*.gen_assert*.tlul_assert.maskMustBeCont*}
113fvdisable {*xbar_main.u_*.tlul_assert_*.gen_assert*.tlul_assert.addressAlignedToSize*}
114fvdisable {*xbar_main.u_*.tlul_assert_*.gen_assert*.tlul_assert.legal*}
115fvdisable {*xbar_main.u_*.tlul_assert_*.gen_assert*.tlul_assert.sizeMatches*}
116
117# top_earlgrey
118fvdisable {top_earlgrey.*addressAligned*}
119fvdisable {top_earlgrey.*tlul_assert*Must*}
120fvdisable {top_earlgrey.*onlyOne*}
121fvdisable {top_earlgrey.*Response*}
122fvdisable {top_earlgrey.*legal*}
123fvdisable {top_earlgrey.u_xbar_main.u_sm1_*.rspIdInRange}
124fvdisable {top_earlgrey.u_xbar_main.*depthShall*}
125fvdisable {top_earlgrey.u_xbar_main.*tlul_assert*DataKnown*}
126fvdisable {top_earlgrey.u_dm_top.*tlul_assert_*DataKnown*}
127
128#-------------------------------------------------------------------------
129# Configure grid usage
130#-------------------------------------------------------------------------
Cindy Chenc37f6972020-06-24 14:25:02 -0700131# Use "set_grid_usage" option to launch the run on the grid.
Will Chen4af6c252020-03-12 11:30:59 -0700132# Use option "-type <LSF|RTDA|SGE>=<# of workers>" to specify the type of grid and the numbers of workers
Cindy Chenc37f6972020-06-24 14:25:02 -0700133# "-control {<submission commands>} is used to specify the exact qsub/bsub string to use for accessing the grid resources
134# Ex: set_grid_usage -type sge=12 -control { qsub -P <machine name> }
Will Chen4af6c252020-03-12 11:30:59 -0700135set_grid_usage -type RSH=12
136
137#-------------------------------------------------------------------------
Cindy Chenc37f6972020-06-24 14:25:02 -0700138# Run all the assertion and cover properties
Will Chen4af6c252020-03-12 11:30:59 -0700139#-------------------------------------------------------------------------
140# time limit set to 2 hours
141set_fml_var fml_max_time 2H
142
Cindy Chenc37f6972020-06-24 14:25:02 -0700143# initialize the design
Will Chen4af6c252020-03-12 11:30:59 -0700144sim_run -stable
145sim_save_reset
146
147check_fv -block
148
149#-------------------------------------------------------------------------
150# Report
151#-------------------------------------------------------------------------
152# to generate detailed report add "-verbose" option to "report_fv"
153# Ex: report_fv -verbose > ../../../$env(FPV_TOP)_verbose.result
154report_fv > ../../../$env(FPV_TOP).result
155
156#-------------------------------------------------------------------------
157# Generate Formal Coverage
158#-------------------------------------------------------------------------
Cindy Chenc37f6972020-06-24 14:25:02 -0700159# VC Formal also provides formal coverage metrics as part of formal signoff flow.
Will Chen4af6c252020-03-12 11:30:59 -0700160# If you would like to generate formal coverage or need any other help, please send email to vcf_support@synopsys.com
161
162quit