Srikrishna Iyer | d1f896e | 2020-03-05 13:52:40 -0800 | [diff] [blame] | 1 | --- |
| 2 | title: "Hardware Dashboard" |
| 3 | --- |
Garret Kelly | 9eebde0 | 2019-10-22 15:36:49 -0400 | [diff] [blame] | 4 | |
Srikrishna Iyer | d1f896e | 2020-03-05 13:52:40 -0800 | [diff] [blame] | 5 | This page serves as the landing spot for all hardware development within the OpenTitan project. |
Garret Kelly | 9eebde0 | 2019-10-22 15:36:49 -0400 | [diff] [blame] | 6 | |
Srikrishna Iyer | 84dac53 | 2020-04-02 21:45:21 -0700 | [diff] [blame] | 7 | We start off by providing links to the [results of various tool-flows](#results-of-toolflows) run on all of our [Comportable]({{< relref "doc/rm/comportability_specification" >}}) IPs. |
Srikrishna Iyer | d1f896e | 2020-03-05 13:52:40 -0800 | [diff] [blame] | 8 | This includes DV simulations, FPV and lint, all of which are run with the `dvsim` tool which serves as the common frontend. |
Garret Kelly | 9eebde0 | 2019-10-22 15:36:49 -0400 | [diff] [blame] | 9 | |
Srikrishna Iyer | d1f896e | 2020-03-05 13:52:40 -0800 | [diff] [blame] | 10 | The [Comportable IPs](#comportable-ips) following it provides links to their design specifications and DV plans, and tracks their current stage of development. |
Sam Elliott | 2061d8b | 2020-04-20 19:56:54 +0100 | [diff] [blame] | 11 | See the [Hardware Development Stages]({{< relref "/doc/project/development_stages.md" >}}) for description of the hardware stages and how they are determined. |
Garret Kelly | 9eebde0 | 2019-10-22 15:36:49 -0400 | [diff] [blame] | 12 | |
Srikrishna Iyer | d1f896e | 2020-03-05 13:52:40 -0800 | [diff] [blame] | 13 | Next, we focus on all available [processor cores](#processor-cores) and provide links to their design specifications, DV plans and the DV simulation results. |
Garret Kelly | 9eebde0 | 2019-10-22 15:36:49 -0400 | [diff] [blame] | 14 | |
Michael Schaffner | c6a47e5 | 2020-04-06 16:35:32 -0700 | [diff] [blame] | 15 | Finally, we provide the same set of information for all available [top level designs](#top-level-designs), including an additional dashboard with preliminary synthesis results for some of these designs. |
Garret Kelly | 9eebde0 | 2019-10-22 15:36:49 -0400 | [diff] [blame] | 16 | |
Garret Kelly | 9eebde0 | 2019-10-22 15:36:49 -0400 | [diff] [blame] | 17 | |
Srikrishna Iyer | d1f896e | 2020-03-05 13:52:40 -0800 | [diff] [blame] | 18 | ## Results of tool-flows |
| 19 | |
| 20 | * [DV simulation summary results, with coverage (nightly)](https://reports.opentitan.org/hw/top_earlgrey/dv/summary.html) |
Cindy Chen | 2b4c82e | 2020-07-07 21:15:01 -0700 | [diff] [blame] | 21 | * [FPV summary results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/fpv/summary.html) |
Srikrishna Iyer | d1f896e | 2020-03-05 13:52:40 -0800 | [diff] [blame] | 22 | * [Lint summary results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/lint/ascentlint/summary.html) |
Michael Schaffner | 51d2d69 | 2020-05-07 10:08:23 -0700 | [diff] [blame] | 23 | * [Style lint summary results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/lint/veriblelint/summary.html) |
Srikrishna Iyer | d1f896e | 2020-03-05 13:52:40 -0800 | [diff] [blame] | 24 | |
| 25 | ## Comportable IPs |
| 26 | |
| 27 | {{< dashboard "hw/ip" >}} |
| 28 | |
| 29 | ## Processor cores |
| 30 | |
| 31 | * `core_ibex` |
| 32 | * [User manual](https://ibex-core.readthedocs.io/en/latest) |
| 33 | * [DV plan](https://ibex-core.readthedocs.io/en/latest/verification.html) |
| 34 | * DV simulation results, with coverage (nightly) (TBD) |
| 35 | |
| 36 | ## Top level designs |
| 37 | |
| 38 | * `top_earlgrey` |
| 39 | * [Design specification]({{< relref "hw/top_earlgrey/doc" >}}) |
| 40 | * DV plan (TBD) |
| 41 | * [DV simulation results, with coverage (nightly)](https://reports.opentitan.org/hw/top_earlgrey/dv/latest/results.html) |
| 42 | * FPV results (nightly) (TBD) |
Michael Schaffner | 51d2d69 | 2020-05-07 10:08:23 -0700 | [diff] [blame] | 43 | * [Lint results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/lint/ascentlint/latest/results.html) |
| 44 | * [Style lint results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/lint/veriblelint/latest/results.html) |
Michael Schaffner | c6a47e5 | 2020-04-06 16:35:32 -0700 | [diff] [blame] | 45 | * [Synthesis results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/syn/latest/results.html) |