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Srikrishna Iyerd1f896e2020-03-05 13:52:40 -08001---
2title: "Hardware Dashboard"
3---
Garret Kelly9eebde02019-10-22 15:36:49 -04004
Srikrishna Iyerd1f896e2020-03-05 13:52:40 -08005This page serves as the landing spot for all hardware development within the OpenTitan project.
Garret Kelly9eebde02019-10-22 15:36:49 -04006
Srikrishna Iyer84dac532020-04-02 21:45:21 -07007We start off by providing links to the [results of various tool-flows](#results-of-toolflows) run on all of our [Comportable]({{< relref "doc/rm/comportability_specification" >}}) IPs.
Srikrishna Iyerd1f896e2020-03-05 13:52:40 -08008This includes DV simulations, FPV and lint, all of which are run with the `dvsim` tool which serves as the common frontend.
Garret Kelly9eebde02019-10-22 15:36:49 -04009
Srikrishna Iyerd1f896e2020-03-05 13:52:40 -080010The [Comportable IPs](#comportable-ips) following it provides links to their design specifications and DV plans, and tracks their current stage of development.
Sam Elliott2061d8b2020-04-20 19:56:54 +010011See the [Hardware Development Stages]({{< relref "/doc/project/development_stages.md" >}}) for description of the hardware stages and how they are determined.
Garret Kelly9eebde02019-10-22 15:36:49 -040012
Srikrishna Iyerd1f896e2020-03-05 13:52:40 -080013Next, we focus on all available [processor cores](#processor-cores) and provide links to their design specifications, DV plans and the DV simulation results.
Garret Kelly9eebde02019-10-22 15:36:49 -040014
Michael Schaffnerc6a47e52020-04-06 16:35:32 -070015Finally, we provide the same set of information for all available [top level designs](#top-level-designs), including an additional dashboard with preliminary synthesis results for some of these designs.
Garret Kelly9eebde02019-10-22 15:36:49 -040016
Garret Kelly9eebde02019-10-22 15:36:49 -040017
Srikrishna Iyerd1f896e2020-03-05 13:52:40 -080018## Results of tool-flows
19
20* [DV simulation summary results, with coverage (nightly)](https://reports.opentitan.org/hw/top_earlgrey/dv/summary.html)
Cindy Chen2b4c82e2020-07-07 21:15:01 -070021* [FPV summary results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/fpv/summary.html)
Srikrishna Iyerd1f896e2020-03-05 13:52:40 -080022* [Lint summary results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/lint/ascentlint/summary.html)
Michael Schaffner51d2d692020-05-07 10:08:23 -070023* [Style lint summary results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/lint/veriblelint/summary.html)
Srikrishna Iyerd1f896e2020-03-05 13:52:40 -080024
25## Comportable IPs
26
27{{< dashboard "hw/ip" >}}
28
29## Processor cores
30
31* `core_ibex`
32 * [User manual](https://ibex-core.readthedocs.io/en/latest)
33 * [DV plan](https://ibex-core.readthedocs.io/en/latest/verification.html)
34 * DV simulation results, with coverage (nightly) (TBD)
35
36## Top level designs
37
38* `top_earlgrey`
39 * [Design specification]({{< relref "hw/top_earlgrey/doc" >}})
40 * DV plan (TBD)
41 * [DV simulation results, with coverage (nightly)](https://reports.opentitan.org/hw/top_earlgrey/dv/latest/results.html)
42 * FPV results (nightly) (TBD)
Michael Schaffner51d2d692020-05-07 10:08:23 -070043 * [Lint results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/lint/ascentlint/latest/results.html)
44 * [Style lint results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/lint/veriblelint/latest/results.html)
Michael Schaffnerc6a47e52020-04-06 16:35:32 -070045 * [Synthesis results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/syn/latest/results.html)