blob: 45e6d0c5d56a704b10a19df947fbffa7dfba86a7 [file] [log] [blame]
Weicai Yangb6007c12019-10-23 18:46:42 -07001// Copyright lowRISC contributors.
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4{
5 name: "uart"
Weicai Yanga0f1ab92020-10-01 17:57:44 -07006 import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
Cindy Chenda227f62021-06-16 10:42:42 -07007 "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
Weicai Yanga0f1ab92020-10-01 17:57:44 -07008 "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
Srikrishna Iyera463e172022-02-02 12:09:39 -08009 "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
10 "uart_sec_cm_testplan.hjson"]
Srikrishna Iyer86169d02021-05-10 09:35:52 -070011 testpoints: [
Weicai Yangb6007c12019-10-23 18:46:42 -070012 {
Cindy Chencef01f52020-11-11 10:11:03 -080013 name: smoke
Weicai Yangb6007c12019-10-23 18:46:42 -070014 desc: '''
Cindy Chencef01f52020-11-11 10:11:03 -080015 - UART smoke test with few bytes transmitted and received asynchronously and
Weicai Yangb6007c12019-10-23 18:46:42 -070016 in parallel with scoreboard checks
17 - TX and RX have 2 independent threads respectively.
18 - program one Tx item in register and wait for it to complete at uart interface,
19 before send another one
20 - sequencally send one Rx byte, then immediately read from register and check it'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070021 stage: V1
Cindy Chencef01f52020-11-11 10:11:03 -080022 tests: ["uart_smoke"]
Weicai Yangb6007c12019-10-23 18:46:42 -070023 }
24 {
25 name: base_random_seq
26 desc: '''
27 - This is the basic sequence that is extended by most of random sequence.
28 - TX and RX have 2 independent threads respectively.
29 - TX: keep programming csr wdata with random delay when fifo isn't full
30 - RX: 2 processes. One is to send item through uart interface when fifo isn't full
31 and the other is to read csr rdata when fifo isn't empty'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070032 stage: V2
Weicai Yangb6007c12019-10-23 18:46:42 -070033 tests: ["uart_tx_rx"]
34 }
35 {
36 name: parity
37 desc: '''Send / receive bytes with parity and odd parity enabled randomly.'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070038 stage: V2
Cindy Chencef01f52020-11-11 10:11:03 -080039 tests: ["uart_smoke", "uart_tx_rx"]
Weicai Yangb6007c12019-10-23 18:46:42 -070040 }
41 {
42 name: parity_error
43 desc: '''
44 - Enable parity and randomly set even/odd parity
45 - Inject parity error randomly on data sent from rx and ensure the interrupt is
46 raised'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070047 stage: V2
Weicai Yangb6007c12019-10-23 18:46:42 -070048 tests: ["uart_rx_parity_err", "uart_intr"]
49 }
50 {
51 name: watermark
52 desc: '''
53 - Program random tx/rx fifo watermark level and keep sending random tx/rx data
54 to fifo.
55 - As the number of pending data entries in the tx/rx fifo reaches the programmed
56 watermark level (fifo size >= watermark level), ensure that the watermark interrupt
57 is asserted
58 - Ensure interrupt stays asserted until cleared as well as fifo level dropped.
59 The tx/rx watermark interrupt is sticky'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070060 stage: V2
Weicai Yangb6007c12019-10-23 18:46:42 -070061 tests: ["uart_tx_rx", "uart_intr"]
62 }
63 {
64 name: fifo_full
65 desc: '''Send over 32 bytes of data but stop when fifo is full'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070066 stage: V2
Weicai Yangb6007c12019-10-23 18:46:42 -070067 tests: ["uart_fifo_full"]
68 }
69 {
70 name: fifo_overflow
71 desc: '''
72 - Keep sending over 32 bytes of data over tx/rx fifo
73 - Ensure excess data bytes are dropped and check overflow interrupt
74 - This uart_fifo_overflow_vseq is extent from uart_fifo_full_vseq and override the
75 constraint to be able to send data over fifo size'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070076 stage: V2
Weicai Yangb6007c12019-10-23 18:46:42 -070077 tests: ["uart_fifo_overflow"]
78 }
79 {
80 name: fifo_reset
81 desc: '''
82 - Fill up the tx/rx fifo. After a random number of bytes shows up on fifo, reset
83 the fifo and ensure that the remaining data bytes do not show up
84 - this sequence is extent from uart_fifo_overflow_vseq, so it can also reset when fifo
85 is at any level, including full or overflow'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070086 stage: V2
Weicai Yangb6007c12019-10-23 18:46:42 -070087 tests: ["uart_fifo_reset"]
88 }
89 {
90 name: rx_frame_err
91 desc: '''
92 - Inject frame error in parity and non-parity cases by not setting stop bit = 1
93 - Ensure the interrupt gets asserted'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070094 stage: V2
Weicai Yangb6007c12019-10-23 18:46:42 -070095 tests: ["uart_intr"]
96 }
97 {
98 name: rx_break_err
99 desc: '''
100 - Program random number of break detection characters
101 - create a frame error scenario and send random number of 0 bytes
102 - If that random number exceeds the programmed break characters
103 - Ensure that the break_err interrupt is asserted'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700104 stage: V2
Weicai Yangb6007c12019-10-23 18:46:42 -0700105 tests: ["uart_intr"]
106 }
107 {
108 name: rx_timeout
109 desc: '''
110 - Program timeout_ctrl register to randomize the timeout. Send random number of
111 data over rx
112 - Wait until it's about to timeout, then check timeout interrupt doesn't fire. Wait
113 for timeout and check timeout interrupt fires
114 - Wait until it's about to timeout, then use either read csr rdata or send RX item
115 through uart interface to reset timeout timer in order to ensure timeout never
116 fires'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700117 stage: V2
Weicai Yangb6007c12019-10-23 18:46:42 -0700118 tests: ["uart_intr"]
119 }
120 {
121 name: perf
122 desc: '''Run fifo_full_vseq with very small delays'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700123 stage: V2
Weicai Yangb6007c12019-10-23 18:46:42 -0700124 tests: ["uart_perf"]
125 }
126 {
127 name: sys_loopback
128 desc: '''
129 - Enable system looback, then drive uart TX and data will be loopbacked through RX
130 - After loopback is done, uart.RDATA will be equal to the data programmed to
131 uart.WDATA'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700132 stage: V2
Weicai Yangb6007c12019-10-23 18:46:42 -0700133 tests: ["uart_loopback"]
134 }
135 {
136 name: line_loopback
137 desc: '''
138 - Enable line loopback and drive uart_rx with random data and random delay
139 - Check uart_tx has same value as uart_rx. There is not synchronizer register between
140 uart_rx and uart_tx during line loopback'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700141 stage: V2
Weicai Yangb6007c12019-10-23 18:46:42 -0700142 tests: ["uart_loopback"]
143 }
144 {
145 name: rx_noise_filter
146 desc: '''
147 - Use 16x fast clk to sample it, data on uart_rx need to be stable for 3 clocks,
148 otherwise, data change won't be taken
149 - Enable noise filter and drive many glitches. Each glitch doesn't lasts less than
150 3 clocks
151 - Ensure the noise will be filterred out and it doesn't affect next normal
152 transaction'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700153 stage: V2
Weicai Yangb6007c12019-10-23 18:46:42 -0700154 tests: ["uart_noise_filter"]
155 }
156 {
157 name: rx_start_bit_filter
158 desc: '''
159 - Start bit should last for at least half baud clock, otherwise, it will be dropped
160 - It's always enabled. Drive start bit for less than half cycle.
161 - Ensure the start bit will be dropped'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700162 stage: V2
Weicai Yangb6007c12019-10-23 18:46:42 -0700163 tests: ["uart_rx_start_bit_filter"]
164 }
165 {
166 name: tx_overide
167 desc: '''Enable override control and use register programming to drive uart output
168 directly.'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700169 stage: V2
Weicai Yangb6007c12019-10-23 18:46:42 -0700170 tests: ["uart_tx_ovrd"]
171 }
172 {
173 name: rx_oversample
174 desc: '''
175 - Use 16x baud clock to sample uart rx
176 - Drive uart rx with 16 bits value, using 16x baud clock
177 - Read RX oversampled value and ensure it's same as driven value'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700178 stage: V2
Weicai Yangb6007c12019-10-23 18:46:42 -0700179 tests: ["uart_rx_oversample"]
180 }
181 {
Weicai Yanged505022021-06-04 16:46:08 -0700182 name: long_b2b_transfer
183 desc: '''
184 - Reduce delay to fill TX fifo and read RX fifo to ensure back2back transfers
185 - Use long back2back transfer to ensure clock difference won't be accumulated across transactions
186 - Uart monitor checks the clock offset between sender and receiver is never over 1/4 of the period'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700187 stage: V2
Weicai Yanged505022021-06-04 16:46:08 -0700188 tests: ["uart_long_xfer_wo_dly"]
189 }
190 {
Weicai Yangb6007c12019-10-23 18:46:42 -0700191 name: stress_all
192 desc: '''
193 - Combine above sequences in one test to run sequentially, except csr sequence and
194 uart_rx_oversample_vseq (requires zero_delays)
195 - Randomly add reset between each sequence'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700196 stage: V2
Weicai Yangb6007c12019-10-23 18:46:42 -0700197 tests: ["uart_stress_all"]
198 }
199 {
200 name: stress_all_with_reset
201 desc: '''Have random reset in parallel with stress_all and tl_errors sequences'''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700202 stage: V2
Srikrishna Iyer7cf7cad2020-01-08 11:32:53 -0800203 tests: ["uart_stress_all_with_rand_reset"]
Weicai Yangb6007c12019-10-23 18:46:42 -0700204 }
205 ]
Srikrishna Iyer86169d02021-05-10 09:35:52 -0700206
207 covergroups: [
208 {
209 name: foo_cg
210 desc: '''
211 '''
212 }
213 ]
Weicai Yangb6007c12019-10-23 18:46:42 -0700214}