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Hugo McNallyf6298b32023-02-12 14:47:22 +00001# Fpvgen: Initial FPV testbench generation tool
Michael Schaffnerb5a88f22019-11-26 19:43:37 -08002
3# Overview
4
5`fpvgen` is a Python tool that can be used to generate the initial boilerplate code for an FPV testbench.
6It takes as input a SystemVerilog module file representing the top-level of an IP to be tested with FPV, and generates the following folders and files in the output directory (which defaults to `../fpv` with respect to the module file provided):
7```console
8.
9├── fpv // default output folder
10│   ├── <ip-name>_fpv.core
11│   ├── tb
12│   │   ├── <ip-name>_bind_fpv.sv
13│   │   └── <ip-name>_fpv.sv
14│   └── vip
15│   └── <ip-name>_assert_fpv.sv
16└── rtl // folder containing the SV module file
17    ├── <ip-name>.sv
18 ...
19```
20The `<ip-name>_fpv.sv` is the FPV testbench that can be used to instantiate different parameterizations of the DUT to be tested.
21`<ip-name>_bind_fpv.sv` contains the bind statement which binds the verification IP `<ip-name>_assert_fpv.sv` to all DUT instances.
22If the IP is flagged as being comportable using the `-c` switch, the CSR FPV assertions are bound to the module as well.
23
24# Examples
25Generating a non-comportable IP can be done as follows (using the LFSR as an example):
26```console
27util/fpvgen.py hw/ip/prim/rtl/prim_lfsr.sv
28```
29
30If the IP is comportable, only the `-c` switch has to be added.
31E.g., using the `pinmux` comportable IP as an example:
32```console
33util/fpvgen.py -c hw/ip/pinmux/rtl/pinmux.sv
34```
35
36If needed, the default output directory can be overridden using the `-o` switch.
37
38# Help Output
39This is the help output from the tool (switch `-h`).
40```console
41usage: fpvgen [-h] [-o OUTDIR] [-c] file
42
43 Boilerplate code generator for FPV testbenches. Can be used for
44 comportable or non-comportable IPs.
45
46 The generator creates the FuseSoC core file and two additional
47 subfolders 'tb' and 'vip' in the output directory. It will place stubs
48 for the testbench and bind files into the 'tb' subfolder, and a stub for
49 the FPV assertions into the 'vip' (verification IP) subfolder.
50
51 The generator needs the path to the top-level module of the IP to be
52 tested. E.g., suppose we would like to generate an FPV testbench for a
53 FIFO primitive located at 'hw/ip/prim/rtl/prim_fifo_sync.sv' we can
54 invoke the generator as follows:
55
56 util/fpvgen.py hw/ip/prim/rtl/prim_fifo_sync.sv
57
58 By default, the output directory is assumed to be '../fpv' with respect
59 to the toplevel module, but this can be overriden using the -eo switch.
60
61 Further if the IP is comportable, this can be indicated using the -c
62 switch, which causes the generator to add a bind statement for the CSR
63 FPV assertions in the testbench.
64
65positional arguments:
66 file Relative path to the SystemVerilog file of the module
67 for which the code shall be generated. This can be a
68 primitive or a comportable IP (for which the -c switch
69 should be set).
70
71optional arguments:
72 -h, --help show this help message and exit
73 -o OUTDIR, --outdir OUTDIR
74 Path where to place the testbench code. This is
75 defaults to '../fpv' w.r.t. to the module path. For
76 instance, if the module path is
77 'hw/ip/mymod/rtl/mymod.sv', the FPV testbench would be
78 generated under hw/ip/mymod/fpv.
79 -c, --is_cip Indicates whether this is a comportable IP. If yes,
80 FPV assertions for the TL-UL interface and CSRs are
81 automatically bound in the testbench. Note however
82 that these CSR assertions need to be generated
83 separately using the regtool automation.
84```