blob: 5e7b9a133df880d45e1ee6e7537606fae945c4a5 [file] [log] [blame]
Chris Frantz340e6232021-08-25 15:56:28 -07001# Copyright lowRISC contributors.
2# Licensed under the Apache License, Version 2.0, see LICENSE for details.
3# SPDX-License-Identifier: Apache-2.0
Chris Frantz6da32ea2021-11-22 13:12:08 -08004
Chris Frantz00c717b2022-07-28 14:58:32 -07005load("@rules_pkg//pkg:mappings.bzl", "pkg_files")
Chris Frantz6da32ea2021-11-22 13:12:08 -08006load("//rules:fusesoc.bzl", "fusesoc_build")
7
Miles Dai99f50442022-05-09 18:44:19 -04008# This configuration exposes fusesoc's "verilator_options" option to the
9# command line. This is intended to allow CI to specifically build a single
Drew Macraeacfd5d02022-10-31 22:39:44 -040010# -threaded Verilated model to suit it's resource constraints.
11# By default, the Verilated model should be built to
Miles Dai99f50442022-05-09 18:44:19 -040012# run with 4 threads.
13load("@bazel_skylib//rules:common_settings.bzl", "string_list_flag")
14
15string_list_flag(
16 name = "verilator_options",
17 build_setting_default = [
18 "--threads",
19 "4",
20 ],
21)
22
Drew Macraeacfd5d02022-10-31 22:39:44 -040023# This configuration exposes fusesoc's "make_options" to enable parallel
24# compilation of the verilated model. Compilation takes about 30m of cpu time
25# and 5m of time that isn't parallelized by this option, so this should reduce
26# the total runtime to ~12m.
27string_list_flag(
28 name = "make_options",
29 build_setting_default = [
30 "-j",
31 "4",
32 ],
33)
34
Chris Frantz6da32ea2021-11-22 13:12:08 -080035fusesoc_build(
Miguel Young de la Sota634aceb2022-04-21 13:38:37 -040036 name = "verilator_real",
Chris Frantz6da32ea2021-11-22 13:12:08 -080037 srcs = [
38 ":all_files",
39 ],
40 cores = [
41 "//:cores",
42 ],
Chris Frantz96e00542021-12-15 13:21:15 -080043 data = ["//hw/ip/otbn:all_files"],
Drew Macraeacfd5d02022-10-31 22:39:44 -040044 make_options = ":make_options",
Chris Frantz00c717b2022-07-28 14:58:32 -070045 output_groups = {
46 "binary": ["sim-verilator/Vchip_sim_tb"],
47 },
Chris Frantz6da32ea2021-11-22 13:12:08 -080048 systems = ["lowrisc:dv:chip_verilator_sim"],
Dan McArdle96444522022-10-18 17:30:39 -040049 tags = [
50 "manual",
51 "verilator",
52 ],
Chris Frantz6da32ea2021-11-22 13:12:08 -080053 target = "sim",
Miles Dai99f50442022-05-09 18:44:19 -040054 verilator_options = ":verilator_options",
Chris Frantz6da32ea2021-11-22 13:12:08 -080055)
56
Chris Frantz00c717b2022-07-28 14:58:32 -070057filegroup(
58 name = "verilator_bin",
59 srcs = [":verilator_real"],
60 output_group = "binary",
61)
62
Miguel Young de la Sota634aceb2022-04-21 13:38:37 -040063# This is used in CI steps that do not want to run Verilator tests, and thus
Drew Macraeacfd5d02022-10-31 22:39:44 -040064# do not want to build the Verilated model. This causes the //hw:verilator
Drew Macraeb549cf32022-10-12 15:47:02 -040065# target to not emit any files, which will break any tests that rely on this;
66# builds will succeed, tests will fail.
Miguel Young de la Sota634aceb2022-04-21 13:38:37 -040067config_setting(
68 name = "disable_verilator_build",
69 values = {"define": "DISABLE_VERILATOR_BUILD=true"},
70)
71
72genrule(
73 name = "verilator_stub",
Chris Frantz00c717b2022-07-28 14:58:32 -070074 outs = ["Vfake_sim_tb"],
Miguel Young de la Sota634aceb2022-04-21 13:38:37 -040075 cmd = """
Chris Frantz00c717b2022-07-28 14:58:32 -070076 script=$@
Miguel Young de la Sota634aceb2022-04-21 13:38:37 -040077 echo '#!/bin/bash' > $$script
78 echo 'echo "ERROR: sim_verilator tests cannot be run when --define DISABLE_VERILATOR_BUILD=true is set!"' >> $$script
79 echo 'echo "This indicates an error in your Bazel invokation"' >> $$script
80 echo 'exit 1' >> $$script
Chris Frantz00c717b2022-07-28 14:58:32 -070081 chmod +x $@
Miguel Young de la Sota634aceb2022-04-21 13:38:37 -040082 """,
83)
84
85alias(
86 name = "verilator",
87 actual = select({
Chris Frantz00c717b2022-07-28 14:58:32 -070088 ":disable_verilator_build": ":verilator_stub",
89 "//conditions:default": ":verilator_bin",
Miguel Young de la Sota634aceb2022-04-21 13:38:37 -040090 }),
Drew Macrae4c178cd2022-05-06 14:42:29 -040091 tags = ["verilator"],
Miguel Young de la Sota634aceb2022-04-21 13:38:37 -040092 visibility = ["//visibility:public"],
93)
94
Eunchan Kim00ea4c72022-06-09 16:46:41 -070095genrule(
96 name = "fusesoc_ignore",
97 outs = ["FUSESOC_IGNORE"],
98 cmd = """
99 touch $@
100 """,
101 visibility = ["//visibility:public"],
102)
103
Chris Frantz0b548fa2021-11-22 14:08:11 -0800104# TODO(lowRISC/opentitan#7972): Globbing all of the //hw/... hierarchy together
105# is a bit of a hack. Longer term, we need proper rules for expressing the
106# relationships between verilog components.
Chris Frantz6da32ea2021-11-22 13:12:08 -0800107filegroup(
108 name = "all_files",
Timothy Trippelba225de2022-11-01 11:32:01 -0700109 srcs = glob(
110 ["**"],
111 # TODO(lowRISC/opentitan#15882): make Verilator work with foundry repo present.
112 exclude = ["foundry/**"],
113 ) + [
Chris Frantz6da32ea2021-11-22 13:12:08 -0800114 "//hw/ip:all_files",
115 "//hw/top_earlgrey:all_files",
116 ],
Miguel Young de la Sota634aceb2022-04-21 13:38:37 -0400117 visibility = ["//visibility:public"],
Chris Frantz6da32ea2021-11-22 13:12:08 -0800118)
Chris Frantz00c717b2022-07-28 14:58:32 -0700119
120pkg_files(
121 name = "package",
122 srcs = ["verilator_bin"],
123 prefix = "earlgrey/verilator",
124 visibility = ["//visibility:public"],
125)