| Weicai Yang | a495d20 | 2019-12-05 15:36:27 -0800 | [diff] [blame] | 1 | CAPI=2: |
| 2 | # Copyright lowRISC contributors. |
| 3 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| 4 | # SPDX-License-Identifier: Apache-2.0 |
| 5 | # |
| 6 | # xbar_${xbar.name}_sim core file generated by `tlgen.py` tool |
| 7 | name: "lowrisc:dv:xbar_${xbar.name}_sim:0.1" |
| 8 | description: "XBAR DV sim target" |
| 9 | filesets: |
| 10 | files_dv: |
| 11 | depend: |
| 12 | - lowrisc:ip:xbar_${xbar.name} |
| 13 | - lowrisc:dv:dv_utils |
| 14 | - lowrisc:dv:xbar_tb |
| 15 | files: |
| 16 | - xbar_${xbar.name}_bind.sv |
| 17 | - tb__xbar_connect.sv: {is_include_file: true} |
| 18 | - xbar_env_pkg__params.sv: {is_include_file: true} |
| 19 | file_type: systemVerilogSource |
| 20 | |
| 21 | targets: |
| 22 | sim: |
| 23 | toplevel: xbar_tb_top |
| 24 | filesets: |
| 25 | - files_dv |
| 26 | default_tool: vcs |
