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opensecura / 3p / lowrisc / opentitan / 2a2508f6b52c6485fc57518a25e5832302abf92e / . / hw / _index.md
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Srikrishna Iyerd1f896e2020-03-05 13:52:40 -0800[diff] [blame]1---
2title: "Hardware Dashboard"
Tobias Wölfelc75c5a12020-09-23 13:12:07 +0200[diff] [blame]3aliases: [/doc/project/hw_dashboard/]
Srikrishna Iyerd1f896e2020-03-05 13:52:40 -0800[diff] [blame]4---
Garret Kelly9eebde02019-10-22 15:36:49 -0400[diff] [blame]5
Srikrishna Iyerd1f896e2020-03-05 13:52:40 -0800[diff] [blame]6This page serves as the landing spot for all hardware development within the OpenTitan project.
Garret Kelly9eebde02019-10-22 15:36:49 -0400[diff] [blame]7
Srikrishna Iyer84dac532020-04-02 21:45:21 -0700[diff] [blame]8We start off by providing links to the [results of various tool-flows](#results-of-toolflows) run on all of our [Comportable]({{< relref "doc/rm/comportability_specification" >}}) IPs.
Srikrishna Iyerd1f896e2020-03-05 13:52:40 -0800[diff] [blame]9This includes DV simulations, FPV and lint, all of which are run with the `dvsim` tool which serves as the common frontend.
Garret Kelly9eebde02019-10-22 15:36:49 -0400[diff] [blame]10
Rasmus Madsenc0b7bd12020-12-09 17:58:10 +0100[diff] [blame]11The [Comportable IPs](#comportable-ips) following it provides links to their design specifications and DV documents, and tracks their current stage of development.
Sam Elliott2061d8b2020-04-20 19:56:54 +0100[diff] [blame]12See the [Hardware Development Stages]({{< relref "/doc/project/development_stages.md" >}}) for description of the hardware stages and how they are determined.
Garret Kelly9eebde02019-10-22 15:36:49 -0400[diff] [blame]13
Rasmus Madsenc0b7bd12020-12-09 17:58:10 +0100[diff] [blame]14Next, we focus on all available [processor cores](#processor-cores) and provide links to their design specifications, DV documents and the DV simulation results.
Garret Kelly9eebde02019-10-22 15:36:49 -0400[diff] [blame]15
Michael Schaffnerc6a47e52020-04-06 16:35:32 -0700[diff] [blame]16Finally, we provide the same set of information for all available [top level designs](#top-level-designs), including an additional dashboard with preliminary synthesis results for some of these designs.
Garret Kelly9eebde02019-10-22 15:36:49 -0400[diff] [blame]17
Garret Kelly9eebde02019-10-22 15:36:49 -0400[diff] [blame]18
Srikrishna Iyerd1f896e2020-03-05 13:52:40 -0800[diff] [blame]19## Results of tool-flows
20
21* [DV simulation summary results, with coverage (nightly)](https://reports.opentitan.org/hw/top_earlgrey/dv/summary.html)
Cindy Chenbfa37b12021-05-24 16:09:01 -0700[diff] [blame]22* [FPV summary results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/formal/summary.html)
Michael Schaffner41a67502020-07-27 19:44:01 -0700[diff] [blame]23* [AscentLint summary results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/lint/ascentlint/summary.html)
24* [Verilator lint summary results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/lint/verilator/summary.html)
Michael Schaffner51d2d692020-05-07 10:08:23 -0700[diff] [blame]25* [Style lint summary results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/lint/veriblelint/summary.html)
Michael Schaffnerc6583ab2020-08-03 15:48:03 -0700[diff] [blame]26* [DV Style lint summary results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/dv/lint/veriblelint/summary.html)
Cindy Chen363bea22020-11-02 19:55:01 -0800[diff] [blame]27* [FPV Style lint summary results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/fpv/lint/veriblelint/summary.html)
Srikrishna Iyerd1f896e2020-03-05 13:52:40 -0800[diff] [blame]28
29## Comportable IPs
30
Philipp Wagner8171ede2021-03-15 21:47:01 +0000[diff] [blame]31{{< dashboard "comportable" >}}
Srikrishna Iyerd1f896e2020-03-05 13:52:40 -0800[diff] [blame]32
33## Processor cores
34
35* `core_ibex`
36 * [User manual](https://ibex-core.readthedocs.io/en/latest)
Srikrishna Iyereab29d12021-08-13 16:01:20 -0700[diff] [blame]37 * [DV document](https://ibex-core.readthedocs.io/en/latest/03_reference/verification.html)
Srikrishna Iyerd1f896e2020-03-05 13:52:40 -0800[diff] [blame]38 * DV simulation results, with coverage (nightly) (TBD)
39
Philipp Wagnercb8c5032021-03-15 21:48:19 +0000[diff] [blame]40## Earl Grey toplevel design
Srikrishna Iyerd1f896e2020-03-05 13:52:40 -0800[diff] [blame]41
Philipp Wagnercb8c5032021-03-15 21:48:19 +0000[diff] [blame]42* [Design specification]({{< relref "hw/top_earlgrey/doc" >}})
43* [DV document]({{< relref "hw/top_earlgrey/doc/dv" >}})
44* [DV simulation results, with coverage (nightly)](https://reports.opentitan.org/hw/top_earlgrey/dv/latest/results.html)
45* [Connectivity results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/conn/jaspergold/latest/results.html)
46* [AscentLint results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/lint/ascentlint/latest/results.html)
47* [Verilator lint results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/lint/verilator/latest/results.html)
48* [Style lint results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/lint/veriblelint/latest/results.html)
49* [DV Style lint results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/dv/lint/veriblelint/latest/results.html)
50* [Synthesis results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/syn/latest/results.html)
Michael Schaffner491cd642021-12-07 17:44:16 -0800[diff] [blame]51* [CDC results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/cdc/latest/results.html)
Philipp Wagnercb8c5032021-03-15 21:48:19 +0000[diff] [blame]52
53### Earl Grey-specific comportable IPs
54
55{{< dashboard "top_earlgrey" >}}
Tobias Wölfel8930a282020-06-09 14:45:53 +0200[diff] [blame]56
57## Hardware documentation overview
58
59{{% sectionContent %}}