| Garret Kelly | 5396f20 | 2019-11-01 14:55:35 -0400 | [diff] [blame] | 1 | --- |
| 2 | title: "List of Top-Level Designs" |
| 3 | --- |
| lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 4 | |
| 5 | This page lists all top-level designs and their targets that are contained within this repository. |
| 6 | Click on the design name to get more information about the design. |
| 7 | |
| Garret Kelly | 5396f20 | 2019-11-01 14:55:35 -0400 | [diff] [blame] | 8 | | Design | Internal Name | Simulation Targets | FPGA Targets | ASIC Targets | Description | |
| 9 | |--------|---------------|--------------------|--------------|--------------|-------------| |
| 10 | | [Earl Grey]({{< relref "hw/top_earlgrey/doc" >}}) | `top_earlgrey` | Verilator | Nexys Video\* | *None yet.* | 0.1 release | |
| lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 11 | |
| 12 | A `*` behind an FPGA board indicates it can be used with a free EDA tool license. |
