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opensecura / 3p / lowrisc / opentitan / 1671f81706a73b0079d0ca00813f6a52115304d1 / . / sw / device / lib / dif / dif_otbn.md
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Sam Elliottf72a4be2020-08-28 12:28:04 +0100[diff] [blame]1---
2title: "OTBN DIF Checklist"
3---
4
5This checklist is for [Development Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [OTBN DIF]({{< relref "hw/ip/otbn/doc" >}}).
6All checklist items refer to the content in the [Checklist]({{< relref "/doc/project/checklist.md" >}}).
7
Timothy Trippel4f9a3332022-02-16 16:00:29 -0800[diff] [blame]8<h2>DIF Checklist</h2>
Sam Elliottf72a4be2020-08-28 12:28:04 +0100[diff] [blame]9
Timothy Trippel4f9a3332022-02-16 16:00:29 -0800[diff] [blame]10<h3>S1</h3>
Sam Elliottf72a4be2020-08-28 12:28:04 +0100[diff] [blame]11
12Type | Item | Resolution | Note/Collaterals
13---------------|----------------------|-------------|------------------
Philipp Wagnere2a05582020-11-05 11:36:44 +0000[diff] [blame]14Implementation | [DIF_EXISTS][] | Done |
15Implementation | [DIF_USED_IN_TREE][] | Done |
Sam Elliottf8456182020-11-19 12:21:30 +0000[diff] [blame]16Tests | [DIF_TEST_SMOKE][] | Done |
Sam Elliottf72a4be2020-08-28 12:28:04 +0100[diff] [blame]17
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]18[DIF_EXISTS]: {{< relref "/doc/project/checklist.md#dif_exists" >}}
19[DIF_USED_IN_TREE]: {{< relref "/doc/project/checklist.md#dif_used_in_tree" >}}
Sam Elliottf8456182020-11-19 12:21:30 +0000[diff] [blame]20[DIF_TEST_SMOKE]: {{< relref "/doc/project/checklist.md#dif_test_smoke" >}}
Sam Elliottf72a4be2020-08-28 12:28:04 +0100[diff] [blame]21
Timothy Trippel4f9a3332022-02-16 16:00:29 -0800[diff] [blame]22<h3>S2</h3>
Sam Elliottf72a4be2020-08-28 12:28:04 +0100[diff] [blame]23
24Type | Item | Resolution | Note/Collaterals
25---------------|-----------------------------|-------------|------------------
Timothy Trippel4f9a3332022-02-16 16:00:29 -0800[diff] [blame]26Coordination | [DIF_HW_FEATURE_COMPLETE][] | Done | [HW Dashboard]({{< relref "hw" >}})
27Implementation | [DIF_FEATURES][] | Done |
28Coordination | [DIF_DV_TESTS][] | Done |
Sam Elliottf72a4be2020-08-28 12:28:04 +0100[diff] [blame]29
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]30[DIF_HW_FEATURE_COMPLETE]: {{< relref "/doc/project/checklist.md#dif_hw_feature_complete" >}}
Timothy Trippel4f9a3332022-02-16 16:00:29 -0800[diff] [blame]31[DIF_FEATURES]: {{< relref "/doc/project/checklist.md#dif_features" >}}
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]32[DIF_DV_TESTS]: {{< relref "/doc/project/checklist.md#dif_dv_tests" >}}
Sam Elliottf72a4be2020-08-28 12:28:04 +0100[diff] [blame]33
Timothy Trippel4f9a3332022-02-16 16:00:29 -0800[diff] [blame]34<h3>S3</h3>
Sam Elliottf72a4be2020-08-28 12:28:04 +0100[diff] [blame]35
36Type | Item | Resolution | Note/Collaterals
37---------------|----------------------------------|-------------|------------------
38Coordination | [DIF_HW_DESIGN_COMPLETE][] | Not Started |
39Coordination | [DIF_HW_VERIFICATION_COMPLETE][] | Not Started |
Timothy Trippel4f9a3332022-02-16 16:00:29 -0800[diff] [blame]40Documentation | [DIF_DOC_HW][] | Not Started |
41Code Quality | [DIF_CODE_STYLE][] | Not Started |
42Tests | [DIF_TEST_UNIT][] | Done |
Sam Elliottf72a4be2020-08-28 12:28:04 +0100[diff] [blame]43Review | [DIF_TODO_COMPLETE][] | Not Started |
Sam Elliottf72a4be2020-08-28 12:28:04 +0100[diff] [blame]44Review | Reviewer(s) | Not Started |
45Review | Signoff date | Not Started |
46
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]47[DIF_HW_DESIGN_COMPLETE]: {{< relref "/doc/project/checklist.md#dif_hw_design_complete" >}}
48[DIF_HW_VERIFICATION_COMPLETE]: {{< relref "/doc/project/checklist.md#dif_hw_verification_complete" >}}
Timothy Trippel4f9a3332022-02-16 16:00:29 -0800[diff] [blame]49[DIF_DOC_HW]: {{< relref "/doc/project/checklist.md#dif_doc_hw" >}}
50[DIF_CODE_STYLE]: {{< relref "/doc/project/checklist.md#dif_code_style" >}}
51[DIF_TEST_UNIT]: {{< relref "/doc/project/checklist.md#dif_test_unit" >}}
Michael Schaffner945bbef2020-10-09 19:20:39 -0700[diff] [blame]52[DIF_TODO_COMPLETE]: {{< relref "/doc/project/checklist.md#dif_todo_complete" >}}