Port Width Fixes: Required for syn

Synopsys synthesis will not resolve port mismatches in real time and
mismatches therefore result in matcha syn runs failing.

This CL topic fixes port width mismatches in wherever they're seen by
synopsys tools. VCS build.log has been the most useful resource for
finding these.

A separate CL:1600 in opensecura 3p/ip/isp was also made in an effort to
fix port mismatches.
https://opensecura-review.git.corp.google.com/c/3p/ip/isp/+/1600

Change-Id: I59c4ca80f14fffa01172cd0b3b43f111da2abcea

hw/ip/rv_dm/data/rv_dm.hjson

diff --git a/hw/ip/rv_dm/data/rv_dm.hjson b/hw/ip/rv_dm/data/rv_dm.hjson
index b2c1ba8..9042ff4 100644
--- a/hw/ip/rv_dm/data/rv_dm.hjson
+++ b/hw/ip/rv_dm/data/rv_dm.hjson
@@ -90,7 +90,7 @@
       type:    "uni"
       name:    "unavailable"
       act:     "rcv"
-      default: "2'b0"
+      default: "3'b0"
       desc:    '''
                This signal indicates to the debug module that the main processor is not available
                for debug (e.g. due to a low-power state).