| commit | feb9da73235fc52c099904f4645905ac34560e87 | [log] [tgz] |
|---|---|---|
| author | Jaedon Kim <jdonjdon@google.com> | Fri Aug 12 23:30:57 2022 +0000 |
| committer | Timothy Trippel <5633066+timothytrippel@users.noreply.github.com> | Mon Aug 22 11:55:33 2022 -0700 |
| tree | c39191785d32bff2ba064d56f5969d12a02985c4 | |
| parent | a1d24f32d4f7cbfd1d04c45bf67453db335d75fb [diff] |
[chip,dv,pwrmgr] fix pwrmgr_deep_sleep_all_reset_reqs
This test is timed out for multiple reasons.
r1. SV sequence wait for either hw por or sysrst to generate
external reset triggering event.
But event gets randomized and these two event are not
always show up at the c test. This can causes timeout event
at the sv sequence.
r2. Another issue was from the c test, after the test prints
a LOG_INFO sv sequence is waiting for, if the c test put another
LOG_INFO, before sv sequence goes back to the beginning of the loop,
sv sequence misses the LOG_INFO.
This PR address those two issues as below.
1. Create dummy wait state in sv sequence s.t. the number of iteration
is same as the c test.
This can remove spurious timeout event cause by r1.
2. Add wait 'SwTestStatusInBootRom' at the end of sv loop s.t.
loop in c and sv in sync at each iteration.
Signed-off-by: Jaedon Kim <jdonjdon@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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