| commit | a1d24f32d4f7cbfd1d04c45bf67453db335d75fb | [log] [tgz] |
|---|---|---|
| author | Weicai Yang <weicai@google.com> | Thu Aug 18 17:13:54 2022 -0700 |
| committer | weicaiyang <49293026+weicaiyang@users.noreply.github.com> | Mon Aug 22 11:47:54 2022 -0700 |
| tree | eea36fdcc3543ed12d527da18b0ebecfdcb5e0d6 | |
| parent | a16aaea1ff90387bde585a6f968b8e2ba2ea7b2b [diff] |
[spi_device/dv] Test flash mode read buffer 1. add `spi_device_flash_mode_vseq` to enable flash_mode 2. update scb 1. add upstream_spi_req_fifo to get the item when opcode and address are collected 2. check read command on read buffer while payload is being collected 3. extract `compare_mem_byte` to convert addr and compare with exp mem 3. rename `spi_device_pass_all` to `spi_device_flash_all` as it randomly test flash_mode and passthrough_mode Signed-off-by: Weicai Yang <weicai@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.
Have a look at CONTRIBUTING and our documentation on project organization and processes for guidelines on how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).