hw/ip/edn/dv/edn_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: edn

  // Top level dut name (sv module).
  dut: edn

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: vcs

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:edn_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/ip/edn/data/edn_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/ip/edn/data/edn.hjson"

  // Import additional common sim cfg files.
  // TODO: remove imported cfgs that do not apply.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]

  // Add additional tops for simulation.
  sim_tops: ["edn_bind", "edn_cov_bind",
             "sec_cm_prim_sparse_fsm_flop_bind",
             "sec_cm_prim_count_bind",
             "sec_cm_prim_onehot_check_bind"]

  vcs_cov_excl_files: ["{proj_root}/hw/ip/edn/dv/cov/edn_fsm_excl.el"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  // Default UVM test and seq class name.
  uvm_test: edn_base_test
  uvm_test_seq: edn_base_vseq

  run_opts: ["+cdc_instrumentation_enabled=1"]

  // List of test specifications.
  tests: [
    {
      name: edn_smoke
      uvm_test: edn_smoke_test
      uvm_test_seq: edn_smoke_vseq
    }

    {
      name: edn_regwen
      uvm_test: edn_smoke_test
      uvm_test_seq: edn_regwen_vseq
      reseed: 10
    }

    {
      name: edn_genbits
      uvm_test: edn_genbits_test
      uvm_test_seq: edn_genbits_vseq
    }

    {
      name: edn_stress_all
      uvm_test: edn_stress_all_test
      uvm_test_seq: edn_stress_all_vseq
    }

    {
      name: edn_stress_all_with_rand_reset
      uvm_test: edn_stress_all_test
    }

    {
      name: edn_intr
      uvm_test: edn_intr_test
      uvm_test_seq: edn_intr_vseq
    }

    {
      name: edn_alert
      uvm_test: edn_alert_test
      uvm_test_seq: edn_alert_vseq
    }

    {
      name: edn_err
      uvm_test: edn_intr_test
      uvm_test_seq: edn_err_vseq
    }

    {
      name: edn_disable
      uvm_test: edn_disable_test
      uvm_test_seq: edn_disable_vseq
      // For debug purpose, this test is very short.
      run_opts: ["+test_timeout_ns=100_000"]
    }

    {
      name: edn_disable_auto_req_mode
      uvm_test: edn_disable_auto_req_mode_test
      uvm_test_seq: edn_disable_auto_req_mode_vseq
      // For debug purpose, this test is very short.
      run_opts: ["+test_timeout_ns=500_000"]
    }
  ]

  // List of regressions.
  regressions: [
    {
      name: smoke
      tests: ["edn_smoke"]
    }
  ]
}