[prim_fifo_sync] Fix DC synth issue related to unpacked array

Signed-off-by: Michael Schaffner <msf@opentitan.org>

hw/ip/prim/rtl/prim_fifo_sync.sv

diff --git a/hw/ip/prim/rtl/prim_fifo_sync.sv b/hw/ip/prim/rtl/prim_fifo_sync.sv
index 206abd2..aac7cc5 100644
--- a/hw/ip/prim/rtl/prim_fifo_sync.sv
+++ b/hw/ip/prim/rtl/prim_fifo_sync.sv
@@ -110,7 +110,7 @@
 
     // the generate blocks below are needed to avoid lint errors due to array indexing
     // in the where the fifo only has one storage element
-    logic [Width-1:0] storage [Depth];
+    logic [Depth-1:0][Width-1:0] storage;
     logic [Width-1:0] storage_rdata;
     if (Depth == 1) begin : gen_depth_eq1
       assign storage_rdata = storage[0];